Simulation Results: kmac/unmasked

 
23/05/2026 11:52:00 DVSim: v1.49.0 sha: 21f062e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.81 %
  • code
  • 92.39 %
  • assert
  • 98.80 %
  • func
  • 96.25 %
  • line
  • 97.66 %
  • branch
  • 95.95 %
  • cond
  • 94.77 %
  • toggle
  • 100.00 %
  • FSM
  • 73.55 %
Validation stages
V1
100.00%
V2
97.66%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 61.450s 4594.487us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.520s 122.374us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.580s 61.168us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 13.080s 866.592us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 9.140s 1764.311us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 3.180s 534.565us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.580s 61.168us 20 20 100.00
kmac_csr_aliasing 9.140s 1764.311us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.180s 22.408us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.750s 27.806us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 4975.490s 761235.513us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 947.340s 145201.002us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2521.570s 450648.275us 5 5 100.00
kmac_test_vectors_sha3_256 2333.660s 211728.258us 5 5 100.00
kmac_test_vectors_sha3_384 1552.430s 323327.505us 5 5 100.00
kmac_test_vectors_sha3_512 1255.200s 660375.922us 5 5 100.00
kmac_test_vectors_shake_128 199.740s 65415.188us 5 5 100.00
kmac_test_vectors_shake_256 2450.840s 102903.372us 5 5 100.00
kmac_test_vectors_kmac 3.690s 312.793us 5 5 100.00
kmac_test_vectors_kmac_xof 2.900s 96.503us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 416.780s 66979.282us 50 50 100.00
app 50 50 100.00
kmac_app 306.120s 64009.038us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 283.580s 71975.214us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 338.610s 79976.378us 50 50 100.00
error 50 50 100.00
kmac_error 386.780s 48329.710us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 12.970s 4200.755us 50 50 100.00
sideload_invalid 32 50 64.00
kmac_sideload_invalid 110.380s 10117.204us 32 50 64.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 46.100s 2283.887us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 39.070s 21029.849us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 65.980s 27471.668us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 42.730s 629.893us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 2152.220s 200079.432us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.200s 16.740us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.240s 21.837us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 3.860s 154.835us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 3.860s 154.835us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.520s 122.374us 5 5 100.00
kmac_csr_rw 1.580s 61.168us 20 20 100.00
kmac_csr_aliasing 9.140s 1764.311us 5 5 100.00
kmac_same_csr_outstanding 3.160s 125.766us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.520s 122.374us 5 5 100.00
kmac_csr_rw 1.580s 61.168us 20 20 100.00
kmac_csr_aliasing 9.140s 1764.311us 5 5 100.00
kmac_same_csr_outstanding 3.160s 125.766us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.460s 72.803us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.460s 72.803us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.460s 72.803us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.460s 72.803us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 6.040s 308.561us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_sec_cm 80.010s 18127.836us 5 5 100.00
kmac_tl_intg_err 6.170s 378.093us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 6.170s 378.093us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 42.730s 629.893us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 61.450s 4594.487us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 416.780s 66979.282us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.460s 72.803us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 80.010s 18127.836us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 80.010s 18127.836us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 80.010s 18127.836us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 61.450s 4594.487us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 42.730s 629.893us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 80.010s 18127.836us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 280.280s 64946.375us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 61.450s 4594.487us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
kmac_stress_all_with_rand_reset 328.830s 20160.798us 5 10 50.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) 3 test runs
kmac_sideload_invalid 70554062301021140709643626079784834459345693965633452006730147473727629863377 81
UVM_INFO @ 10051605018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 49933835986665239410939858380422882256428086367735688395096240280175120184196 82
UVM_INFO @ 10033207260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 26415875937865935337233522265242405738643699657386550394312963543938306387466 81
UVM_INFO @ 10598326991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
kmac_stress_all_with_rand_reset 92972792099370809418073987187062892039620747069113606157921349354718020625325 217
UVM_INFO @ 11540814088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 92867948806161371654036757197279214321822315263148248523299771815623709924159 121
UVM_INFO @ 1389383719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 103357234934335664056518036881691382171358653063423882497308776895050002395899 290
UVM_INFO @ 19884778140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:858) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) 2 test runs
kmac_stress_all_with_rand_reset 6436211047134606085040744773335620956845223622122946053899916790706845160816 267
UVM_INFO @ 6905332322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 11887447147137269897457297170080340801242152721010911507208981563240988811820 419
UVM_INFO @ 25276637358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) 2 test runs
kmac_sideload_invalid 84660416019386659740343783168271187368384723756708867560285818775031743182670 78
UVM_INFO @ 10021617337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 51823730568554037365858714392928984434528928574040757990311313908260117519072 78
UVM_INFO @ 10037513926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) 2 test runs
kmac_sideload_invalid 66002167844078053058543027427808475740918793339963496049523443101881521023975 88
UVM_INFO @ 10335408431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 41330271230478090106887559569482212328772013656114739564543575168939874086395 90
UVM_INFO @ 10325095830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) 2 test runs
kmac_sideload_invalid 48793192795267903335774880411884707254202965109623093367753853170133489838184 79
UVM_INFO @ 10230832595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 102769969120280353902910316175068009333949380585160937667366274535819249302236 79
UVM_INFO @ 10022516599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) 2 test runs
kmac_sideload_invalid 81837576872233413938379247011837157715726188916569787458865053321980218456663 95
UVM_INFO @ 10244514288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 44952383230495910006903559329199749581713910920631196943574687433889994273740 92
UVM_INFO @ 10357748216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) 1 test run
kmac_sideload_invalid 74636579371439958773930690024087176063154491151063852327424858423736391560850 90
UVM_INFO @ 10206014985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) 1 test run
kmac_sideload_invalid 69496309400386591322540094909285605661580346664428794650505933981529471129618 89
UVM_INFO @ 10151389333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) 1 test run
kmac_sideload_invalid 47337827851961857699229629619295578801004115048482234931807576282338071638479 81
UVM_INFO @ 10095847697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) 1 test run
kmac_sideload_invalid 80994995586963888268059490640669825984670727349198059884004625493189074347259 85
UVM_INFO @ 10126645536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) 1 test run
kmac_sideload_invalid 11344467232935817765888069578064741349369056661150903904140267187836750312464 93
UVM_INFO @ 10117203827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) 1 test run
kmac_sideload_invalid 33955713219050770225784420801431751443222992354848244512266072102472270109916 83
UVM_INFO @ 10845552700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) 1 test run
kmac_sideload_invalid 114994775947378125494296112287352090622571427903371373330171280707326574413607 95
UVM_INFO @ 10127378897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---