Simulation Results: lc_ctrl/volatile_unlock_disabled

 
23/05/2026 11:52:00 DVSim: v1.49.0 sha: 21f062e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.65 %
  • code
  • 86.35 %
  • assert
  • 94.97 %
  • func
  • 96.62 %
  • line
  • 97.28 %
  • branch
  • 94.14 %
  • cond
  • 81.63 %
  • toggle
  • 89.54 %
  • FSM
  • 69.16 %
Validation stages
V1
100.00%
V2
99.18%
V2S
100.00%
V3
42.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 7.210s 167.915us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.600s 19.730us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.610s 19.261us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 3.480s 186.019us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 1.810s 80.538us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.470s 109.603us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.610s 19.261us 20 20 100.00
lc_ctrl_csr_aliasing 1.810s 80.538us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 8.820s 561.784us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 15.870s 325.257us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.300s 33.494us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 4.390s 735.818us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 12.300s 667.346us 50 50 100.00
lc_errors 48 50 96.00
lc_ctrl_errors 14.460s 2581.390us 48 50 96.00
security_escalation 258 260 99.23
lc_ctrl_state_failure 12.300s 667.346us 50 50 100.00
lc_ctrl_prog_failure 4.390s 735.818us 50 50 100.00
lc_ctrl_errors 14.460s 2581.390us 48 50 96.00
lc_ctrl_security_escalation 12.180s 2798.881us 50 50 100.00
lc_ctrl_jtag_state_failure 63.360s 10637.922us 20 20 100.00
lc_ctrl_jtag_prog_failure 23.260s 3839.761us 20 20 100.00
lc_ctrl_jtag_errors 87.650s 18992.392us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_smoke 9.640s 587.209us 20 20 100.00
lc_ctrl_jtag_state_post_trans 28.060s 4514.047us 20 20 100.00
lc_ctrl_jtag_prog_failure 23.260s 3839.761us 20 20 100.00
lc_ctrl_jtag_errors 87.650s 18992.392us 20 20 100.00
lc_ctrl_jtag_access 23.130s 5012.993us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 25.080s 4562.901us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 2.180s 156.634us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.500s 198.606us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 31.720s 7012.939us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 32.050s 1395.882us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.540s 22.445us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.150s 189.109us 10 10 100.00
lc_ctrl_jtag_alert_test 2.330s 98.611us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 46.490s 22772.633us 10 10 100.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 1.490s 14.391us 50 50 100.00
stress_all 46 50 92.00
lc_ctrl_stress_all 357.310s 14472.480us 46 50 92.00
alert_test 50 50 100.00
lc_ctrl_alert_test 1.890s 69.903us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 4.730s 246.886us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 4.730s 246.886us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.600s 19.730us 5 5 100.00
lc_ctrl_csr_rw 1.610s 19.261us 20 20 100.00
lc_ctrl_csr_aliasing 1.810s 80.538us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.220s 46.042us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.600s 19.730us 5 5 100.00
lc_ctrl_csr_rw 1.610s 19.261us 20 20 100.00
lc_ctrl_csr_aliasing 1.810s 80.538us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.220s 46.042us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_sec_cm 10.180s 587.077us 5 5 100.00
lc_ctrl_tl_intg_err 3.260s 255.938us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 3.260s 255.938us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 15.870s 325.257us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 12.300s 667.346us 50 50 100.00
lc_ctrl_sec_cm 10.180s 587.077us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 12.300s 667.346us 50 50 100.00
lc_ctrl_sec_cm 10.180s 587.077us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 12.300s 667.346us 50 50 100.00
lc_ctrl_sec_cm 10.180s 587.077us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 12.300s 667.346us 50 50 100.00
lc_ctrl_sec_cm 10.180s 587.077us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 12.300s 667.346us 50 50 100.00
lc_ctrl_sec_cm 10.180s 587.077us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 12.300s 667.346us 50 50 100.00
lc_ctrl_sec_cm 10.180s 587.077us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 12.300s 667.346us 50 50 100.00
lc_ctrl_sec_cm 10.180s 587.077us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 12.300s 667.346us 50 50 100.00
lc_ctrl_sec_cm 10.180s 587.077us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 12.180s 2798.881us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 8.820s 561.784us 50 50 100.00
lc_ctrl_jtag_state_post_trans 28.060s 4514.047us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 15.340s 492.407us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 15.340s 492.407us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 18.220s 3212.497us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 13.280s 4802.756us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 13.280s 4802.756us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 21 50 42.00
lc_ctrl_stress_all_with_rand_reset 119.120s 17797.608us 21 50 42.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 23 test runs
lc_ctrl_stress_all_with_rand_reset 93188592755178845727094275916362042367592685813767798142928396572624826263879 6881
UVM_INFO @ 3682090659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 48779561841804272479133981524975830146206646604673178629907988263712708975658 1331
UVM_INFO @ 1724694131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 69863341653304430869475788148864675241486866339121264408510285277584547901705 1055
UVM_INFO @ 1111176364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 59483465715325525438121752508086600539483836594052859612211318689157138751044 1591
UVM_INFO @ 2079678042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 89717303085808666659562920601190511388072185544360515723770389065678521389773 150
UVM_INFO @ 423230232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 21778681730477490229936297406773350397000647614540081633245639955351591410163 1124
UVM_INFO @ 2045492801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 28314851116155491196860366679353697230456274003252648173250574993448634397762 6120
UVM_INFO @ 2639038011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 90088381206391141699082741452745851894733125114418500317251206709191292205534 1814
UVM_INFO @ 3252824655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 15292258253797999988816105898943561441593408874610949986005944103086200301851 161
UVM_INFO @ 1094624326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 84538526886196664597519417705207312388603575969768548145452881777659926366645 150
UVM_INFO @ 221696442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 48433503497755476495600078205898872457905788572753513330619273533718534452304 4192
UVM_INFO @ 1328466043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 132783780161544498195874853415246431252004133117338524959019758780338536280 8414
UVM_INFO @ 7389053813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 110951423938388239440232004852930518772281778879492993286396019635951212063099 1754
UVM_INFO @ 15494769158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 112918558613787731915477317133260532633277030226529694086577166051212971603703 3757
UVM_INFO @ 4437984616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 95749115284766498756285973131775801596551820771320405327523722461962895205771 150
UVM_INFO @ 7179697390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 95514031789640023427798545238808476377128168126589921000534087575698725754770 1677
UVM_INFO @ 3037902555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 104784253948818503143335776603991034222387862253682778406791251205284151263639 2893
UVM_INFO @ 15877825051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 16393199363512427065584780752466668401091803519851737142594907421599660864734 3183
UVM_INFO @ 8508529118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 1025135824874422009413598782419543449016799078071652970388978828979578646 2676
UVM_INFO @ 391656483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 81102041633988485032951934541811410651100550416829771969508628877632306499769 2845
UVM_INFO @ 3008410244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 62898258645161152032020058178338933789998686669221876910765842776824117816131 6313
UVM_INFO @ 8603605384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 69619857553938581928095362000974789158819303139349468688168731579391970425845 504
UVM_INFO @ 1726342269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 75542053665049665664022614056546344074843139874020256321632272527398818318240 297
UVM_INFO @ 336316009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 7 test runs
lc_ctrl_stress_all 108363570172943427780972690667068766248056054721397464966396481829184498774000 7945
UVM_INFO @ 5952996771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 37619553557564910112126543813352485479795613047792420152012195644288086310977 4537
UVM_INFO @ 2250521416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 102302284255964133558372470889650156479190526258229882419859626281577256301042 487
UVM_INFO @ 235244946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 64763080441147433205737404522232900848252708892741342720156265777519648059256 2772
UVM_INFO @ 5740443289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 112527863975357206182100734364490633104729407394674914767193940282299184137355 3327
UVM_INFO @ 10991059674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 56636476123095267368020739909232218334473983330401242156814490763184581281988 716
UVM_INFO @ 179378104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 46386067051635368129942906074430623456066275540343003199853277226845373556611 1070
UVM_INFO @ 74126563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:923) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 3 test runs
lc_ctrl_stress_all_with_rand_reset 77786495717953172142993548034294786061525949017192350202767920945256320989762 7392
UVM_INFO @ 3541116744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 96342294971401166454219564725824333899215662741977292436562622227190481484339 8801
UVM_INFO @ 17797608177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 56878998827774488231993050618007895962360506843216943358834387058832814874688 4726
UVM_INFO @ 14668831919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* 2 test runs
lc_ctrl_stress_all 81120857644706467974735548821637623214089644237934941310270429338840589741736 3096
UVM_INFO @ 19551525659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 72921956324610025994691483140055538390653446785219645187519798659413987077368 9209
UVM_INFO @ 318020929555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---