Simulation Results: lc_ctrl/volatile_unlock_enabled

 
23/05/2026 11:52:00 DVSim: v1.49.0 sha: 21f062e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.62 %
  • code
  • 86.63 %
  • assert
  • 94.97 %
  • func
  • 96.26 %
  • line
  • 97.26 %
  • branch
  • 94.24 %
  • cond
  • 82.04 %
  • toggle
  • 89.54 %
  • FSM
  • 70.09 %
Validation stages
V1
100.00%
V2
99.32%
V2S
100.00%
V3
48.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 7.360s 2109.546us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.280s 22.623us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.390s 26.328us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 2.970s 206.102us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 1.330s 19.790us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.740s 119.221us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.390s 26.328us 20 20 100.00
lc_ctrl_csr_aliasing 1.330s 19.790us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 7.330s 1066.069us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 12.360s 495.920us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.330s 14.532us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 4.360s 203.299us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 12.880s 310.719us 50 50 100.00
lc_errors 48 50 96.00
lc_ctrl_errors 12.260s 1847.454us 48 50 96.00
security_escalation 258 260 99.23
lc_ctrl_state_failure 12.880s 310.719us 50 50 100.00
lc_ctrl_prog_failure 4.360s 203.299us 50 50 100.00
lc_ctrl_errors 12.260s 1847.454us 48 50 96.00
lc_ctrl_security_escalation 10.580s 770.204us 50 50 100.00
lc_ctrl_jtag_state_failure 63.590s 6142.336us 20 20 100.00
lc_ctrl_jtag_prog_failure 15.080s 3067.745us 20 20 100.00
lc_ctrl_jtag_errors 66.360s 19106.293us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_smoke 8.920s 497.190us 20 20 100.00
lc_ctrl_jtag_state_post_trans 21.950s 1915.463us 20 20 100.00
lc_ctrl_jtag_prog_failure 15.080s 3067.745us 20 20 100.00
lc_ctrl_jtag_errors 66.360s 19106.293us 20 20 100.00
lc_ctrl_jtag_access 13.720s 751.902us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 25.290s 2622.675us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 4.580s 977.804us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.120s 73.816us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 14.550s 1061.885us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 11.740s 1391.182us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.400s 66.524us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.160s 289.536us 10 10 100.00
lc_ctrl_jtag_alert_test 1.810s 54.747us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 28.930s 10118.516us 10 10 100.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 1.480s 95.035us 50 50 100.00
stress_all 47 50 94.00
lc_ctrl_stress_all 475.190s 31774.530us 47 50 94.00
alert_test 50 50 100.00
lc_ctrl_alert_test 1.910s 47.261us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 5.040s 262.384us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 5.040s 262.384us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.280s 22.623us 5 5 100.00
lc_ctrl_csr_rw 1.390s 26.328us 20 20 100.00
lc_ctrl_csr_aliasing 1.330s 19.790us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.800s 203.466us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.280s 22.623us 5 5 100.00
lc_ctrl_csr_rw 1.390s 26.328us 20 20 100.00
lc_ctrl_csr_aliasing 1.330s 19.790us 5 5 100.00
lc_ctrl_same_csr_outstanding 1.800s 203.466us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_sec_cm 7.670s 249.110us 5 5 100.00
lc_ctrl_tl_intg_err 3.940s 1357.174us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 3.940s 1357.174us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 12.360s 495.920us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 12.880s 310.719us 50 50 100.00
lc_ctrl_sec_cm 7.670s 249.110us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 12.880s 310.719us 50 50 100.00
lc_ctrl_sec_cm 7.670s 249.110us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 12.880s 310.719us 50 50 100.00
lc_ctrl_sec_cm 7.670s 249.110us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 12.880s 310.719us 50 50 100.00
lc_ctrl_sec_cm 7.670s 249.110us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 12.880s 310.719us 50 50 100.00
lc_ctrl_sec_cm 7.670s 249.110us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 12.880s 310.719us 50 50 100.00
lc_ctrl_sec_cm 7.670s 249.110us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 12.880s 310.719us 50 50 100.00
lc_ctrl_sec_cm 7.670s 249.110us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 12.880s 310.719us 50 50 100.00
lc_ctrl_sec_cm 7.670s 249.110us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 10.580s 770.204us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 7.330s 1066.069us 50 50 100.00
lc_ctrl_jtag_state_post_trans 21.950s 1915.463us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 13.090s 633.247us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 13.090s 633.247us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 13.670s 660.224us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 14.510s 769.244us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 14.510s 769.244us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 24 50 48.00
lc_ctrl_stress_all_with_rand_reset 128.830s 8957.500us 24 50 48.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 23 test runs
lc_ctrl_stress_all_with_rand_reset 95115285000802757846396427976647176155105697664680056950863156688228369201148 155
UVM_INFO @ 285588159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 71043524219507436221683739258510081575591145482662249586072520715019195526976 6434
UVM_INFO @ 20731392578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 37707041778349383586899081365126339678846683274027710751330869375090685996463 514
UVM_INFO @ 981686682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 55916399558205705911782353088596765359509867871263522619379686194119743223128 2449
UVM_INFO @ 5701300219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 20950057920693695145698718956146319031583468655619140408159758905267216569171 196
UVM_INFO @ 470262827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 16896365146969254295565127146344646186228698018988982230141167005600787583072 2304
UVM_INFO @ 10691874868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 19241046534884502822729461859095535971802351870562588208001045173279207049240 150
UVM_INFO @ 215449195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 7816624168455410194225617248608681961798089353685922583987468531719764354791 10381
UVM_INFO @ 86691861081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 45700627249451912755672989682484358764915870122186487112466112320158059795011 3359
UVM_INFO @ 3081839664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 429957618700101202045302228994353811327956602955328448122123906018794357248 196
UVM_INFO @ 205156542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 95762127183572985076110468870514323952338142082899398773192093948651036116568 835
UVM_INFO @ 7146895170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 92144918598732976708523173367559115219282305730907824340529565388378902435681 151
UVM_INFO @ 108942009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 24686509705192548216081070652379811292967543044164524909325496894250467542855 5634
UVM_INFO @ 1102559637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 76329125212074652099447959504431858160550614010840285028211694016536150155521 160
UVM_INFO @ 4003429510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 89529614500576403033132476405143596026088438726744458669744719317556637965923 10492
UVM_INFO @ 3889742466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 8226594002276766986094496904619252552540490519070451476784966326646850964582 6536
UVM_INFO @ 12494854823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 60268932309811045271691190283453890638962745597868033660065746233428611336389 10050
UVM_INFO @ 3471064871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 115564872712519189572452896423795934196818579952351109589674429819886862506722 5538
UVM_INFO @ 8838800900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 93657195777126247202454866800002955402920672786740431320543919860082178092113 1294
UVM_INFO @ 2783032889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 41237932967570282917312004469844591715559218427767125714059856594872261114725 278
UVM_INFO @ 711468931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 45904590656020202729042575090325917448508475176859563491266497237536374790649 5324
UVM_INFO @ 7702333715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 9603601966075933203609243550845333112873034407691252638581023269187974779822 151
UVM_INFO @ 1495564388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 107162450057033721784695384315041624356495912558280553729808601589777998367687 1433
UVM_INFO @ 2152222296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 4 test runs
lc_ctrl_errors 95394718903677094848897168325108051439676804814361187810490395365815924773156 3530
UVM_INFO @ 1765627652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 86403214251528428203797055701680201338802833207924784587007389005039852335487 2679
UVM_INFO @ 320153548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 7852513504952846865635852470788933271531380735948400780718749754859930010952 1792
UVM_INFO @ 718234580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 16290380634522315568861120503943826469084258552231208971562441594140224214651 7718
UVM_INFO @ 13463681487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:923) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 3 test runs
lc_ctrl_stress_all_with_rand_reset 2797846068575760759615940101422862191418509913180995909180096792883693298913 10578
UVM_INFO @ 21210836535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 81806396954492846847144966022610182606926848572628169726133995906737915427969 1090
UVM_INFO @ 2311633522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 87929287764537106420168239707543978997062586529751833555641564098495124410632 2198
UVM_INFO @ 4057501096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* 1 test run
lc_ctrl_stress_all 60375661637898287363596742793187855648827429678046113308890121759971599989720 2525
UVM_INFO @ 37084040933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---