Simulation Results: otbn

 
23/05/2026 11:52:00 DVSim: v1.49.0 sha: 21f062e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.92 %
  • code
  • 95.75 %
  • assert
  • 98.00 %
  • func
  • 100.00 %
  • block
  • 99.47 %
  • line
  • 99.61 %
  • branch
  • 93.21 %
  • toggle
  • 90.17 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.91%
V2S
98.53%
V3
40.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 37.000s 77.119us 1 1 100.00
single_binary 100 100 100.00
otbn_single 77.000s 393.655us 100 100 100.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 37.000s 28.432us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 36.000s 30.189us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 39.000s 331.502us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 36.000s 56.922us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 41.000s 69.834us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 36.000s 30.189us 20 20 100.00
otbn_csr_aliasing 36.000s 56.922us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 164.000s 33857.160us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 80.000s 4665.320us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 53.000s 81.460us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 78.000s 161.714us 1 1 100.00
back_to_back 9 10 90.00
otbn_multi 501.000s 2167.503us 9 10 90.00
stress_all 10 10 100.00
otbn_stress_all 207.000s 571.087us 10 10 100.00
lc_escalation 59 60 98.33
otbn_escalate 43.000s 59.130us 59 60 98.33
zero_state_err_urnd 4 5 80.00
otbn_zero_state_err_urnd 35.000s 57.450us 4 5 80.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 35.000s 19.674us 10 10 100.00
alert_test 50 50 100.00
otbn_alert_test 37.000s 68.373us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 36.000s 42.708us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 36.000s 124.876us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 36.000s 124.876us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 37.000s 28.432us 5 5 100.00
otbn_csr_rw 36.000s 30.189us 20 20 100.00
otbn_csr_aliasing 36.000s 56.922us 5 5 100.00
otbn_same_csr_outstanding 36.000s 20.469us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 37.000s 28.432us 5 5 100.00
otbn_csr_rw 36.000s 30.189us 20 20 100.00
otbn_csr_aliasing 36.000s 56.922us 5 5 100.00
otbn_same_csr_outstanding 36.000s 20.469us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 37.000s 68.552us 10 10 100.00
otbn_dmem_err 36.000s 63.869us 15 15 100.00
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 35.000s 58.281us 5 5 100.00
otbn_controller_ispr_rdata_err 36.000s 131.197us 5 5 100.00
otbn_mac_bignum_acc_err 32.000s 12.502us 5 5 100.00
otbn_urnd_err 34.000s 31.457us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 31.000s 70.984us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 32.000s 44.087us 2 2 100.00
otbn_non_sec_partial_wipe 10 10 100.00
otbn_partial_wipe 33.000s 30.991us 10 10 100.00
tl_intg_err 25 25 100.00
otbn_sec_cm 283.000s 5238.919us 5 5 100.00
otbn_tl_intg_err 49.000s 601.339us 20 20 100.00
passthru_mem_tl_intg_err 20 20 100.00
otbn_passthru_mem_tl_intg_err 94.000s 219.422us 20 20 100.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 283.000s 5238.919us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 283.000s 5238.919us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 37.000s 77.119us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 36.000s 63.869us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 37.000s 68.552us 10 10 100.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 49.000s 601.339us 20 20 100.00
sec_cm_controller_fsm_global_esc 59 60 98.33
otbn_escalate 43.000s 59.130us 59 60 98.33
sec_cm_controller_fsm_local_esc 39 40 97.50
otbn_imem_err 37.000s 68.552us 10 10 100.00
otbn_dmem_err 36.000s 63.869us 15 15 100.00
otbn_zero_state_err_urnd 35.000s 57.450us 4 5 80.00
otbn_illegal_mem_acc 31.000s 70.984us 5 5 100.00
otbn_sec_cm 283.000s 5238.919us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 283.000s 5238.919us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 77.000s 393.655us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 37.000s 68.552us 10 10 100.00
otbn_dmem_err 36.000s 63.869us 15 15 100.00
otbn_zero_state_err_urnd 35.000s 57.450us 4 5 80.00
otbn_illegal_mem_acc 31.000s 70.984us 5 5 100.00
otbn_sec_cm 283.000s 5238.919us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 283.000s 5238.919us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 59 60 98.33
otbn_escalate 43.000s 59.130us 59 60 98.33
sec_cm_start_stop_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 37.000s 68.552us 10 10 100.00
otbn_dmem_err 36.000s 63.869us 15 15 100.00
otbn_zero_state_err_urnd 35.000s 57.450us 4 5 80.00
otbn_illegal_mem_acc 31.000s 70.984us 5 5 100.00
otbn_sec_cm 283.000s 5238.919us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 283.000s 5238.919us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 77.000s 393.655us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 31.000s 16.846us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 33.000s 89.373us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 115.000s 2217.577us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 115.000s 2217.577us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 32.000s 52.273us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 283.000s 5238.919us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 283.000s 5238.919us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 9 10 90.00
otbn_rf_bignum_intg_err 37.000s 209.959us 9 10 90.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 283.000s 5238.919us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 283.000s 5238.919us 5 5 100.00
sec_cm_loop_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 34.000s 119.869us 4 5 80.00
sec_cm_call_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 34.000s 119.869us 4 5 80.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 31.000s 27.639us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 77.000s 393.655us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 77.000s 393.655us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 77.000s 393.655us 100 100 100.00
sec_cm_write_mem_integrity 9 10 90.00
otbn_multi 501.000s 2167.503us 9 10 90.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 77.000s 393.655us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 77.000s 393.655us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 40.000s 43.497us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 77.000s 393.655us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 283.000s 5238.919us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
otbn_stress_all_with_rand_reset 504.000s 7288.649us 4 10 40.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 35.000s 40.080us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
otbn_stress_all_with_rand_reset 7739651327827485041520028445699339343048328378823871565828370608048517122964 297
UVM_INFO @ 391497658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 76849687684703819806501155616535874687604628236001995376301610499460622705874 562
UVM_INFO @ 7288649319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 11763145351838359249929069101063032493301204414565196751726263319358658112596 156
UVM_INFO @ 123125698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 61092046354658110559256950572761175031196626314513568445004730749540221738611 335
UVM_INFO @ 805598283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 2 test runs
otbn_zero_state_err_urnd 13454939443161968086417671742378944914911751127221306935544893396510569679025 109
UVM_ERROR @ 9789114 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 9789114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stack_addr_integ_chk 38666200638441223686944974572686178899629943076316148561603368229234638929668 126
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 5421133 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 5421133 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 5421133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 63497515708136636648370822680693430276566965381795556051250154693035036746812 269
UVM_INFO @ 793900806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status 1 test run
otbn_escalate 29973950422925696402029417875735319051929750951983538225740397529994819666604 114
UVM_INFO @ 1246741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 1 test run
otbn_multi 47744213937268750321019146672795986955919785357114521834690125100337670535157 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 1 test run
otbn_rf_bignum_intg_err 21437598391319562592064245030906343537783628387378505516428170026721150191668 113
UVM_INFO @ 50413431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 6042512655243032480396419525811917774362328279174324315315782105407619803917 168
UVM_INFO @ 124214322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---