Simulation Results: otp_ctrl

 
23/05/2026 11:52:00 DVSim: v1.49.0 sha: 21f062e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.55 %
  • code
  • 86.38 %
  • assert
  • 95.52 %
  • func
  • 92.74 %
  • line
  • 90.50 %
  • branch
  • 86.99 %
  • cond
  • 94.16 %
  • toggle
  • 95.85 %
  • FSM
  • 64.41 %
Validation stages
V1
97.41%
V2
95.31%
V2S
93.81%
V3
17.82%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.140s 210.262us 1 1 100.00
smoke 50 50 100.00
otp_ctrl_smoke 11.120s 1479.971us 50 50 100.00
csr_hw_reset 5 5 100.00
otp_ctrl_csr_hw_reset 3.570s 1460.283us 5 5 100.00
csr_rw 20 20 100.00
otp_ctrl_csr_rw 2.270s 176.822us 20 20 100.00
csr_bit_bash 5 5 100.00
otp_ctrl_csr_bit_bash 9.020s 1055.012us 5 5 100.00
csr_aliasing 5 5 100.00
otp_ctrl_csr_aliasing 6.420s 401.115us 5 5 100.00
csr_mem_rw_with_rand_reset 17 20 85.00
otp_ctrl_csr_mem_rw_with_rand_reset 5.990s 1733.321us 17 20 85.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otp_ctrl_csr_rw 2.270s 176.822us 20 20 100.00
otp_ctrl_csr_aliasing 6.420s 401.115us 5 5 100.00
mem_walk 5 5 100.00
otp_ctrl_mem_walk 1.550s 140.500us 5 5 100.00
mem_partial_access 5 5 100.00
otp_ctrl_mem_partial_access 1.610s 565.660us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 15.870s 3544.292us 1 1 100.00
init_fail 300 300 100.00
otp_ctrl_init_fail 6.810s 2780.213us 300 300 100.00
partition_check 34 60 56.67
otp_ctrl_background_chks 39.490s 15038.237us 10 10 100.00
otp_ctrl_check_fail 60.890s 10214.619us 24 50 48.00
regwen_during_otp_init 50 50 100.00
otp_ctrl_regwen 14.340s 4661.990us 50 50 100.00
partition_lock 50 50 100.00
otp_ctrl_dai_lock 54.260s 6061.963us 50 50 100.00
interface_key_check 50 50 100.00
otp_ctrl_parallel_key_req 48.690s 22175.243us 50 50 100.00
lc_interactions 250 250 100.00
otp_ctrl_parallel_lc_req 22.370s 8597.996us 50 50 100.00
otp_ctrl_parallel_lc_esc 40.620s 18859.640us 200 200 100.00
otp_dai_errors 48 50 96.00
otp_ctrl_dai_errs 32.780s 3590.193us 48 50 96.00
otp_macro_errors 28 50 56.00
otp_ctrl_macro_errs 46.310s 7734.515us 28 50 56.00
test_access 50 50 100.00
otp_ctrl_test_access 73.780s 34919.062us 50 50 100.00
stress_all 47 50 94.00
otp_ctrl_stress_all 386.300s 58145.759us 47 50 94.00
intr_test 50 50 100.00
otp_ctrl_intr_test 2.590s 609.864us 50 50 100.00
alert_test 50 50 100.00
otp_ctrl_alert_test 3.060s 222.344us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otp_ctrl_tl_errors 6.460s 439.265us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otp_ctrl_tl_errors 6.460s 439.265us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otp_ctrl_csr_hw_reset 3.570s 1460.283us 5 5 100.00
otp_ctrl_csr_rw 2.270s 176.822us 20 20 100.00
otp_ctrl_csr_aliasing 6.420s 401.115us 5 5 100.00
otp_ctrl_same_csr_outstanding 3.360s 1860.703us 20 20 100.00
tl_d_partial_access 50 50 100.00
otp_ctrl_csr_hw_reset 3.570s 1460.283us 5 5 100.00
otp_ctrl_csr_rw 2.270s 176.822us 20 20 100.00
otp_ctrl_csr_aliasing 6.420s 401.115us 5 5 100.00
otp_ctrl_same_csr_outstanding 3.360s 1860.703us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
otp_ctrl_sec_cm 210.220s 177887.438us 5 5 100.00
tl_intg_err 25 25 100.00
otp_ctrl_sec_cm 210.220s 177887.438us 5 5 100.00
otp_ctrl_tl_intg_err 32.430s 20460.947us 20 20 100.00
prim_count_check 5 5 100.00
otp_ctrl_sec_cm 210.220s 177887.438us 5 5 100.00
prim_fsm_check 5 5 100.00
otp_ctrl_sec_cm 210.220s 177887.438us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
otp_ctrl_tl_intg_err 32.430s 20460.947us 20 20 100.00
sec_cm_secret_mem_scramble 50 50 100.00
otp_ctrl_smoke 11.120s 1479.971us 50 50 100.00
sec_cm_part_mem_digest 50 50 100.00
otp_ctrl_smoke 11.120s 1479.971us 50 50 100.00
sec_cm_dai_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 210.220s 177887.438us 5 5 100.00
sec_cm_kdi_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 210.220s 177887.438us 5 5 100.00
sec_cm_lci_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 210.220s 177887.438us 5 5 100.00
sec_cm_part_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 210.220s 177887.438us 5 5 100.00
sec_cm_scrmbl_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 210.220s 177887.438us 5 5 100.00
sec_cm_timer_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 210.220s 177887.438us 5 5 100.00
sec_cm_dai_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 210.220s 177887.438us 5 5 100.00
sec_cm_kdi_seed_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 210.220s 177887.438us 5 5 100.00
sec_cm_kdi_entropy_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 210.220s 177887.438us 5 5 100.00
sec_cm_lci_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 210.220s 177887.438us 5 5 100.00
sec_cm_part_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 210.220s 177887.438us 5 5 100.00
sec_cm_scrmbl_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 210.220s 177887.438us 5 5 100.00
sec_cm_timer_integ_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 210.220s 177887.438us 5 5 100.00
sec_cm_timer_cnsty_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 210.220s 177887.438us 5 5 100.00
sec_cm_timer_lfsr_redun 5 5 100.00
otp_ctrl_sec_cm 210.220s 177887.438us 5 5 100.00
sec_cm_dai_fsm_local_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 40.620s 18859.640us 200 200 100.00
otp_ctrl_sec_cm 210.220s 177887.438us 5 5 100.00
sec_cm_lci_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 40.620s 18859.640us 200 200 100.00
sec_cm_kdi_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 40.620s 18859.640us 200 200 100.00
sec_cm_part_fsm_local_esc 228 250 91.20
otp_ctrl_parallel_lc_esc 40.620s 18859.640us 200 200 100.00
otp_ctrl_macro_errs 46.310s 7734.515us 28 50 56.00
sec_cm_scrmbl_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 40.620s 18859.640us 200 200 100.00
sec_cm_timer_fsm_local_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 40.620s 18859.640us 200 200 100.00
otp_ctrl_sec_cm 210.220s 177887.438us 5 5 100.00
sec_cm_dai_fsm_global_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 40.620s 18859.640us 200 200 100.00
otp_ctrl_sec_cm 210.220s 177887.438us 5 5 100.00
sec_cm_lci_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 40.620s 18859.640us 200 200 100.00
sec_cm_kdi_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 40.620s 18859.640us 200 200 100.00
sec_cm_part_fsm_global_esc 228 250 91.20
otp_ctrl_parallel_lc_esc 40.620s 18859.640us 200 200 100.00
otp_ctrl_macro_errs 46.310s 7734.515us 28 50 56.00
sec_cm_scrmbl_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 40.620s 18859.640us 200 200 100.00
sec_cm_timer_fsm_global_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 40.620s 18859.640us 200 200 100.00
otp_ctrl_sec_cm 210.220s 177887.438us 5 5 100.00
sec_cm_part_data_reg_integrity 300 300 100.00
otp_ctrl_init_fail 6.810s 2780.213us 300 300 100.00
sec_cm_part_data_reg_bkgn_chk 24 50 48.00
otp_ctrl_check_fail 60.890s 10214.619us 24 50 48.00
sec_cm_part_mem_regren 50 50 100.00
otp_ctrl_dai_lock 54.260s 6061.963us 50 50 100.00
sec_cm_part_mem_sw_unreadable 50 50 100.00
otp_ctrl_dai_lock 54.260s 6061.963us 50 50 100.00
sec_cm_part_mem_sw_unwritable 50 50 100.00
otp_ctrl_dai_lock 54.260s 6061.963us 50 50 100.00
sec_cm_lc_part_mem_sw_noaccess 50 50 100.00
otp_ctrl_dai_lock 54.260s 6061.963us 50 50 100.00
sec_cm_access_ctrl_mubi 50 50 100.00
otp_ctrl_dai_lock 54.260s 6061.963us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
otp_ctrl_smoke 11.120s 1479.971us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 50 50 100.00
otp_ctrl_dai_lock 54.260s 6061.963us 50 50 100.00
sec_cm_test_bus_lc_gated 50 50 100.00
otp_ctrl_smoke 11.120s 1479.971us 50 50 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 210.220s 177887.438us 5 5 100.00
sec_cm_direct_access_config_regwen 50 50 100.00
otp_ctrl_regwen 14.340s 4661.990us 50 50 100.00
sec_cm_check_trigger_config_regwen 50 50 100.00
otp_ctrl_smoke 11.120s 1479.971us 50 50 100.00
sec_cm_check_config_regwen 50 50 100.00
otp_ctrl_smoke 11.120s 1479.971us 50 50 100.00
sec_cm_macro_mem_integrity 28 50 56.00
otp_ctrl_macro_errs 46.310s 7734.515us 28 50 56.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 17.150s 7934.178us 1 1 100.00
stress_all_with_rand_reset 17 100 17.00
otp_ctrl_stress_all_with_rand_reset 167.510s 25007.610us 17 100 17.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 58 test runs
otp_ctrl_check_fail 24057706261272237956162996584978271665855189516960829922548450340940884885815 453
UVM_INFO @ 232159844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 41495479369220377500702388576101662883235516808781972754830829308503590088080 1008
UVM_INFO @ 768926425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 32847656007844512882143205916727760909405850208059397351640996766421563899958 1647
UVM_INFO @ 122935586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 26691191794112525220797125971921698836839230850287561097022123328856449821156 8699
UVM_INFO @ 6645713849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 21913651963462865015403721481828690863720730257243019323809656354743174381882 879
UVM_INFO @ 44064527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 81776970883919909407488019428485306540951482093962926338307482064192181642714 5940
UVM_INFO @ 2157513842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 56088893348395130031588132623209329714669914647923098982892759505613676974869 3152
UVM_INFO @ 125387079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 76750739259163823667752496468173687192683776400455485589437625805598348251968 4012
UVM_INFO @ 10135166033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 56752655252060736693336550189842902788873738280768039447674084634219935461647 9031
UVM_INFO @ 532155318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 36549095475660024317801368975587712322292772290420378563897581468564658445064 1091
UVM_INFO @ 2023042766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 11800929554269230437775483244865383166023530641450013865847877267354830719213 8427
UVM_INFO @ 1818408309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 18729314066387676822035026744360125149888492763095868561068842542601794867957 183
UVM_INFO @ 142387366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 73652941348626679146138722213699727579204051221892063140743284143387555452066 7651
UVM_INFO @ 901899722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 91172154156498460259169186684489482304052037259139895940134683217301357706634 5487
UVM_INFO @ 836654878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 16100009959993134009094139879593608051237651171415965178581783150477171494477 739
UVM_INFO @ 210489717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 36859148198537412733088139657603119551003680323572403127628513807076478963152 857
UVM_INFO @ 1603058910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 39568823051427404268528285447520156090415422481888509296943740958170206893528 13061
UVM_INFO @ 2052128329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 51153749501847379054208944032682569321726902363843761435090519669144766755434 631
UVM_INFO @ 173193728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 82891361710165231273481467713413616417969919029061044006989218120164990617917 17737
UVM_INFO @ 843060987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 114425875787085394842621316825197429831663399672309915704068683209431938673864 5603
UVM_INFO @ 7890198788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 101080988088314763809888045469674592159219656793190573220263344557181248744796 5043
UVM_INFO @ 7734514972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 62493082154307405059605605725159778063623116693817743594087069353810529702083 401
UVM_INFO @ 98223115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 97593530253618242037804051198864860850676921410947914760013686900635069346199 519
UVM_INFO @ 382363519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 32320076006629780915530482352440554919837756661857597393430820522330674523092 12562
UVM_INFO @ 840561742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 33834012225468782147087893331949596462226093279517930633547234493883876516075 3607
UVM_INFO @ 65419939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 6307954767051532351906004545754795985046691774984848769844087485864924667739 7769
UVM_INFO @ 227686919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 64468715966018896232490060631366280929794453944818012186108653183268868294918 3086
UVM_INFO @ 245321020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 84584763341347895973579134311539934214325323037925370567608957279748699440972 1955
UVM_INFO @ 73877035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 41646084777355486950593628496580059288452814326371317995394062214340758038373 2622
UVM_INFO @ 188706431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 15404559194697303464061197187540529816649040006896158112815685207231698867169 3459
UVM_INFO @ 393860756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 107692696286678951936250518398997100549332389534776090168315941833860550892782 2053
UVM_INFO @ 592825567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 17002850168910297237149448039546449757126105383819277354467920933516939516573 8260
UVM_INFO @ 1113722628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 82511893202608445121239150402778566399100696208959324214718728673303790996501 859
UVM_INFO @ 949843380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 52347485202756262923052335570394339357754668999727582794513588659799971399822 7719
UVM_INFO @ 423693272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 76645582666546592991472961698367826343503786310252675970421032359266799256334 5044
UVM_INFO @ 2615177914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 46793826495125171891969543548511358900586080289381333125669005042723382822635 6285
UVM_INFO @ 1621095847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 73073581982827884512761851530641731495259118573784111936157668698618752549261 2091
UVM_INFO @ 1788506718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 12151573231195825871823246367093071897170379280260804183572185549318659222612 481
UVM_INFO @ 1048866784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 36206503084934856875479153147335294399818042258146685030638339802247992781627 3478
UVM_INFO @ 1375742385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 9744188382966539751844982718531918769468164905846104692143418346277334233300 8323
UVM_INFO @ 966585373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 99710472152813241328996895975600677412887940767214725493957588854832594400520 6123
UVM_INFO @ 725282554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 2408264002247517393812916126342425320459182717699111279189722698842688522210 2031
UVM_INFO @ 194857962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 92316527866840442221850072504247847311514312208584425106229131757133923629463 3667
UVM_INFO @ 2569331043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 109988734167442932890620510673723046928686617505953529942357056312386293561551 4234
UVM_INFO @ 15506536194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 36492409675343272826210200783205998036699731378005347581330130307986395097192 1816
UVM_INFO @ 400923047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 68481026785889707546127040689282771040755889705576359183564727394465373697137 1693
UVM_INFO @ 130815602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 78718113317959005912331399408828712852429989553727016387418350454849356983325 2934
UVM_INFO @ 436709690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 52046589066139399320945274385309951091809014885775525499454779971782633899429 7481
UVM_INFO @ 11438351414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 93872213066555323757905286727379791752909175899315206691885144177079859549864 517
UVM_INFO @ 408950495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 75567739139455465904467461796564656921326394407304515345299785044658310761288 4634
UVM_INFO @ 127751552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 108161950631141060569287423799069427499455634488195370275872243259455331566915 2547
UVM_INFO @ 3729369446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 76316732540448444588135609322450440702065302234221591018978285006615281677054 63234
UVM_INFO @ 7220280652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 51513837392173893370324534198207072287959639627233053847942677795458437934867 5290
UVM_INFO @ 8610777830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 54348645538482020233737569497514573774505390014996680510975163529195528211039 151
UVM_INFO @ 108989068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 45403043149284298718111001562435337449068480987362890775024661033298401259331 439
UVM_INFO @ 156542242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 100826599929976559862916934278037021798156113775889539743574229543854005176177 22152
UVM_INFO @ 20901072666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 73553970200785983690486821479628206528913843376921550104188410731515119760159 8105
UVM_INFO @ 22230461563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 52799839661520107945453100425095190087851895325109804368238333184447790979263 58279
UVM_INFO @ 7274511884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1825) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 32 test runs
otp_ctrl_stress_all_with_rand_reset 102788816850536285175839759068256163491066241440339242975610023792292190856463 7702
UVM_INFO @ 12478433166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 80275435575454375166447592507981382530091451737034995158014305260904569423389 4100
UVM_INFO @ 6915165159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 10976999929620188883037023073144250541817658779139656415676826156353359456048 92
UVM_INFO @ 53451706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 110664646925741361865011426401388782376373773420767979682342507573868075495798 92
UVM_INFO @ 28931095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 4800409537133900990608449722650908140207974209180760930418957373795836088012 2585
UVM_INFO @ 2439002892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 38963301773448818551899674653730871204111835359818277521743648229879179982481 92
UVM_INFO @ 30836602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 105111824232050690237151984499804568233471993811379335203392463453975733939419 12504
UVM_INFO @ 21668491572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 91286862944155447435964721533166220018655690108891930382943745682811714570821 1657
UVM_INFO @ 323450801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 67470625833184751346189074657119071453806237610570940341746544518152170927775 243
UVM_INFO @ 449783862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 22759775447207914664002106901654264804517118065447776141046916956876495130764 18007
UVM_INFO @ 6358946658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 82268961662176431318678106970993727365134173813023946037702853806673830649917 4020
UVM_INFO @ 13186400319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 60348755275970965901926502420526168622654446205740193244398112383403487398109 39781
UVM_INFO @ 32867089232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 60158399048977831512059664245765077592742716118970703962241995352773333488742 186
UVM_INFO @ 125610611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 22452111880438344995190916430088035080383881186475512476892815359033426605451 10110
UVM_INFO @ 31927612697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 2736607536264719199657986253032311131984257969385194462870527554785844440579 27814
UVM_INFO @ 13326758207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 64718748327326500427446589124637988169538667769517878956009057051574254486400 213
UVM_INFO @ 124466123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 90792782099089787940613828744157710286456856736891074337327192806807794420155 2683
UVM_INFO @ 799513088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 2477099412318824650326172467793857120469146453289174985919606786814706314294 92
UVM_INFO @ 68361784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 16973528013274639023378223995978461329188825055250711474483673930632403410046 92
UVM_INFO @ 426386052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 76125889080664907835064764840670547392935582457092163342100501630167387913305 17297
UVM_INFO @ 766504753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 4211485564838857581399190010220318388032014403646875810916241987897312577604 198
UVM_INFO @ 4879839162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 1764639456591614231779542435725594468571969543918557516341067434147518872101 33716
UVM_INFO @ 1373070549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 78562932834671005390051298339656040726868855805704141425558538381054586625711 16709
UVM_INFO @ 2739825201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 70851509687982275858361688719550550028934409417220830013264042664916109913590 2192
UVM_INFO @ 1463516578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 92636228248809744944722875853456565435583294759734389497224921576911412843510 4482
UVM_INFO @ 4436662424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 112091689177172157094453896721054734069391883020763046857455753789773218823489 8682
UVM_INFO @ 1973609384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 101337446940472138945637406024310424369102735471364529666247607022348347354923 93
UVM_INFO @ 26515993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 73111381894818144602496158010170728488366403624456970828769289763870737915590 36384
UVM_INFO @ 7888183343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 41412977408305420646345339157111181003225391193486385794627278207383191219462 2688
UVM_INFO @ 2555632827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 111824009003050586478581974079259682175689692590241891879196141468966472017590 8835
UVM_INFO @ 3815213207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 111884482483918223850943606275475430393619456156642670379916894762631892932313 18186
UVM_INFO @ 1988958044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 91852459880950395531542963581523767279473483507640198449724981745781455887150 92
UVM_INFO @ 424853092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 22 test runs
otp_ctrl_stress_all_with_rand_reset 104283401306181606460632741804442128891945912192274843567742827892080347296429 23808
UVM_INFO @ 16723254703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 4533732960427831109885832413287383165804217180439285796979636797220741484627 181
UVM_INFO @ 579191271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 43620449993077696409205420615332330681132740853585280628135821801388873371732 9513
UVM_INFO @ 38569053179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 9506667753850300899413299905536424156221599730873667622030316599178958230029 175
UVM_INFO @ 35435859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 77657794568368752167672664355870141759776956210111329463533451024993940196829 14431
UVM_INFO @ 4453673225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 31764242753412404631737593015192982135405965904742158308927919537578040259839 1796
UVM_INFO @ 457474466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 37157295610823050388394502011762920572896063366409002227250480753470811632798 6179
UVM_INFO @ 8649901813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 13893545225787291294095276536446962132803457487204153167677598156273059055505 7195
UVM_INFO @ 8062076645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 29250016572990061301362217230844684428758051756678946376601364181268299068046 13950
UVM_INFO @ 19889710612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 34611074127605648897044157113481091508406883472726044151653745350034426316049 149
UVM_INFO @ 80792392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 97790647905657994194257477151555724114263385604062424374678852389595051653590 12692
UVM_INFO @ 1307019580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 26787577953338125519454077157593945561420530745774295584146071788029099344323 1666
UVM_INFO @ 1307892665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 84696950531770006223085907311489430617756558982416458370702935237578114954788 12643
UVM_INFO @ 40566064329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 85964926930903672374521373319737410650069014916653069892231343235617820241063 5027
UVM_INFO @ 10648561883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 45969204141863909828007127617671328929062216736433909225039815592214062801369 4641
UVM_INFO @ 7558177443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 51732298870376701369530900691104581724074307516411695791040040056477373802663 1357
UVM_INFO @ 333205996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 113032386172168423782366782860336150864462718547856350823111146140771435651724 1336
UVM_INFO @ 343692959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 55666577802369449147938086954925826037466695750709434118791082018787135408794 5671
UVM_INFO @ 1792588237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 57829782547908200672220796913101225283246356378967617282424553255867933366200 145
UVM_INFO @ 55254799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 40324986894790676887669779827889746598610138433362636319484011908965211636433 12396
UVM_INFO @ 4222262879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 33013575405488304479163110328442775422513552674440935371028261846595425570590 26874
UVM_INFO @ 9030923102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 75492816790935530121079728705536691249995581910834593354618519981252393101763 24791
UVM_INFO @ 15618933852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 18 test runs
otp_ctrl_stress_all_with_rand_reset 40859216182816248189728618663175175797753811958572698867159984462151239996850 26256
UVM_INFO @ 9491325467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 48685743267908471661102449829200194482568365700814245443542660748797918116563 92
UVM_INFO @ 55364880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 25291008849744876246004573550947707104652916244757801940049579437357081313035 98
UVM_INFO @ 118510271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 98091973616051500819238999675417065341894338212841992601095170578597406257753 1713
UVM_INFO @ 251745099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 40326425053775103213358178675409030736602655993032642321675386081926963272076 92
UVM_INFO @ 107148010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 95898790147577550705389130325810551166930690844918881743831324699092219376943 92
UVM_INFO @ 56170335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 108105396235023635606500532499157011885853787693651725197012898704215938250149 92
UVM_INFO @ 55718734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 17272461661492160161958947812029306260907996826062352356029897047170404625542 314
UVM_INFO @ 136779434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 31658558309758555614391932141579911617794597802951718809052062566755479576317 1508
UVM_INFO @ 2415858038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 89643728352162632710926361591450250910979373103366955124541995453527589910815 92
UVM_INFO @ 432568768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 13724261201783771916028374571106185044409414789683933490013569675090907121255 17919
UVM_INFO @ 6465247121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 36187968115291222566384253470501679643713083462754713486187823576274136532153 9139
UVM_INFO @ 12956414550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 38495728871140507059258898591457652041528698889597361076387056827331838953275 92
UVM_INFO @ 41845583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 45334149259645608055581451567987372319362203332534850674946046403217567125268 5025
UVM_INFO @ 711892257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 69373516467462362745036960704319544395849416782638134524391412324861535441774 15871
UVM_INFO @ 30749085988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 94259327909321281594627296502302634509723768022057328938515580815539223562838 135
UVM_INFO @ 140745230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 45502613725255616388324436627589465996514970587856219604556308809694178894169 92
UVM_INFO @ 28249356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 37848691403328339048328994911334119345043108045357778250458033161667376216888 92
UVM_INFO @ 433700134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(cio_test_en_o == *)' 2 test runs
otp_ctrl_stress_all_with_rand_reset 103217358430463375224423177035975223098777679068716849048124519599877474114912 4426
UVM_ERROR @ 4956339282 ps: (otp_ctrl_if.sv:297) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 4956339282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 114007906221195822171177909265713259537119598629606943038923653631560666153715 16230
UVM_ERROR @ 4826888132 ps: (otp_ctrl_if.sv:297) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 4826888132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch 2 test runs
otp_ctrl_stress_all_with_rand_reset 16363656698503913546650637246185338934024850793965034962493181289895900715273 92
UVM_INFO @ 2575958968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 107165657842720545742478171901254306248018889964688001414206585738449056802403 95
UVM_INFO @ 8108335573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [otp_ctrl_common_vseq] wait timeout occurred! 1 test run
otp_ctrl_stress_all_with_rand_reset 27830818465213951153581615912055705240616166577262576065330653653707868569869 9431
UVM_INFO @ 11196762758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [otp_ctrl_check_fail_vseq] wait timeout occurred! 1 test run
otp_ctrl_check_fail 3715072678125817718819834011308897138941492804103739194875327065952321863046 2421
UVM_INFO @ 10214618965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen 1 test run
otp_ctrl_stress_all_with_rand_reset 64282467329304802224551166427830623619802117796758780644168013203674067790688 290
UVM_INFO @ 697976714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 1 test run
otp_ctrl_stress_all_with_rand_reset 76951064436347727385742045939668941172666299535397841717700585235220213179777 8339
UVM_INFO @ 6237263687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout otp_ctrl_core_reg_block.status.check_pending (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) 1 test run
otp_ctrl_stress_all_with_rand_reset 7225212206722138540135314436452302552698610452519351990243352749837366622517 8258
UVM_INFO @ 10673600989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---