| V1 |
|
97.50% |
| V2 |
|
97.50% |
| unmapped |
|
70.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| prim_alert_request_test | 78 | 80 | 97.50 | |||
| prim_async_alert | 0.740s | 12.311us | 20 | 20 | 100.00 | |
| prim_async_fatal_alert | 0.750s | 31.337us | 18 | 20 | 90.00 | |
| prim_sync_alert | 0.740s | 10.818us | 20 | 20 | 100.00 | |
| prim_sync_fatal_alert | 0.740s | 27.506us | 20 | 20 | 100.00 | |
| prim_alert_test | 78 | 80 | 97.50 | |||
| prim_async_alert | 0.740s | 12.311us | 20 | 20 | 100.00 | |
| prim_async_fatal_alert | 0.750s | 31.337us | 18 | 20 | 90.00 | |
| prim_sync_alert | 0.740s | 10.818us | 20 | 20 | 100.00 | |
| prim_sync_fatal_alert | 0.740s | 27.506us | 20 | 20 | 100.00 | |
| prim_alert_ping_request_test | 78 | 80 | 97.50 | |||
| prim_async_alert | 0.740s | 12.311us | 20 | 20 | 100.00 | |
| prim_async_fatal_alert | 0.750s | 31.337us | 18 | 20 | 90.00 | |
| prim_sync_alert | 0.740s | 10.818us | 20 | 20 | 100.00 | |
| prim_sync_fatal_alert | 0.740s | 27.506us | 20 | 20 | 100.00 | |
| prim_alert_integrity_errors_test | 78 | 80 | 97.50 | |||
| prim_async_alert | 0.740s | 12.311us | 20 | 20 | 100.00 | |
| prim_async_fatal_alert | 0.750s | 31.337us | 18 | 20 | 90.00 | |
| prim_sync_alert | 0.740s | 10.818us | 20 | 20 | 100.00 | |
| prim_sync_fatal_alert | 0.740s | 27.506us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| prim_alert_init_trigger_test | 78 | 80 | 97.50 | |||
| prim_async_alert | 0.740s | 12.311us | 20 | 20 | 100.00 | |
| prim_async_fatal_alert | 0.750s | 31.337us | 18 | 20 | 90.00 | |
| prim_sync_alert | 0.740s | 10.818us | 20 | 20 | 100.00 | |
| prim_sync_fatal_alert | 0.740s | 27.506us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 14 | 20 | 70.00 | |||
| prim_async_fatal_alert_with_3_cycles_skew | 0.740s | 31.764us | 14 | 20 | 70.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Offending 'alert_o' | 3 test runs | |||
| prim_async_fatal_alert | 83642012906242306062928720904297100468824168628785972335844026875435676956267 | 100 |
UVM_ERROR src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv(320) @ 30510000: reporter [ASSERT FAILED] Alert_A
Starting assertion attempts at time 30579633ps: level = 0 arg = i_alert_receiver.PingDiffOk_A (from inst prim_alert_tb (src/lowrisc_dv_prim_alert_sim_0.1/tb/prim_alert_tb.sv:254))
[prim_alert_seq] Ping signal integrity error sequence finished!
|
|
| prim_async_fatal_alert_with_3_cycles_skew | 94040295032147119914271574651409217018798763398856847603649564155190041605658 | 100 |
UVM_ERROR src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv(320) @ 29994000: reporter [ASSERT FAILED] Alert_A
Starting assertion attempts at time 30063899ps: level = 0 arg = i_alert_receiver.PingDiffOk_A (from inst prim_alert_tb (src/lowrisc_dv_prim_alert_sim_0.1/tb/prim_alert_tb.sv:254))
[prim_alert_seq] Ping signal integrity error sequence finished!
|
|
| prim_async_fatal_alert_with_3_cycles_skew | 100752712205721699510640678854596270500854179445121165829571934371408106817198 | 100 |
UVM_ERROR src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv(320) @ 30451000: reporter [ASSERT FAILED] Alert_A
Starting assertion attempts at time 30541077ps: level = 0 arg = i_alert_receiver.PingDiffOk_A (from inst prim_alert_tb (src/lowrisc_dv_prim_alert_sim_0.1/tb/prim_alert_tb.sv:254))
[prim_alert_seq] Ping signal integrity error sequence finished!
|
|
| Offending 'ping_ok_o' | 3 test runs | |||
| prim_async_fatal_alert | 7330150361950633972734420935261199742097346516577677858468068784788549782369 | 100 |
UVM_ERROR src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv(312) @ 30580000: reporter [ASSERT FAILED] PingResponse1_A
Starting assertion attempts at time 30590451ps: level = 0 arg = i_alert_receiver.PingDiffOk_A (from inst prim_alert_tb (src/lowrisc_dv_prim_alert_sim_0.1/tb/prim_alert_tb.sv:254))
[prim_alert_seq] Ping signal integrity error sequence finished!
|
|
| prim_async_fatal_alert_with_3_cycles_skew | 53878529127841697242335961012642755036208513345892763737447193070311248841147 | 100 |
UVM_ERROR src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv(312) @ 30538000: reporter [ASSERT FAILED] PingResponse1_A
Starting assertion attempts at time 30548138ps: level = 0 arg = i_alert_receiver.PingDiffOk_A (from inst prim_alert_tb (src/lowrisc_dv_prim_alert_sim_0.1/tb/prim_alert_tb.sv:254))
[prim_alert_seq] Ping signal integrity error sequence finished!
|
|
| prim_async_fatal_alert_with_3_cycles_skew | 50576755790698595050545592641403507063269380379113521024855250187647095103751 | 100 |
UVM_ERROR src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv(312) @ 29941000: reporter [ASSERT FAILED] PingResponse1_A
Starting assertion attempts at time 29980519ps: level = 0 arg = i_alert_receiver.PingDiffOk_A (from inst prim_alert_tb (src/lowrisc_dv_prim_alert_sim_0.1/tb/prim_alert_tb.sv:254))
[prim_alert_seq] Ping signal integrity error sequence finished!
|
|
| Offending '$rose(alert_tx_o.alert_p)' | 2 test runs | |||
| prim_async_fatal_alert_with_3_cycles_skew | 109468516208376205971415481395198049346627030638292118139904288357317507899893 | 86 |
UVM_ERROR src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv(334) @ 24199000: reporter [ASSERT FAILED] PingHs_A
[prim_alert_seq] Ping request sequence[0] finished!
[prim_alert_seq] Ping request sequence[1] finished!
[prim_alert_seq] Ping request sequence[2] finished!
|
|
| prim_async_fatal_alert_with_3_cycles_skew | 72558812410879294097516370325032161205121417691669505625087690449288407981409 | 95 |
UVM_ERROR src/lowrisc_prim_alert_0/rtl/prim_alert_sender.sv(334) @ 29056000: reporter [ASSERT FAILED] PingHs_A
[prim_alert_seq] Ping request sequence[9] finished!
Stopping new assertion attempts at time 29445777ps: level = 0 arg = i_alert_receiver.AckDiffOk_A (from inst prim_alert_tb (src/lowrisc_dv_prim_alert_sim_0.1/tb/prim_alert_tb.sv:229))
Starting assertion attempts at time 29575777ps: level = 0 arg = i_alert_receiver.AckDiffOk_A (from inst prim_alert_tb (src/lowrisc_dv_prim_alert_sim_0.1/tb/prim_alert_tb.sv:237))
|
|