| V1 |
|
100.00% |
| V2 |
|
92.46% |
| V2S |
|
100.00% |
| V3 |
|
72.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 50 | 50 | 100.00 | |||
| pwrmgr_smoke | 1.000s | 24.837us | 50 | 50 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| pwrmgr_csr_hw_reset | 1.060s | 27.992us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| pwrmgr_csr_rw | 1.030s | 21.426us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| pwrmgr_csr_bit_bash | 4.440s | 357.750us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| pwrmgr_csr_aliasing | 1.490s | 160.348us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| pwrmgr_csr_mem_rw_with_rand_reset | 1.750s | 68.865us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| pwrmgr_csr_rw | 1.030s | 21.426us | 20 | 20 | 100.00 | |
| pwrmgr_csr_aliasing | 1.490s | 160.348us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| wakeup | 50 | 50 | 100.00 | |||
| pwrmgr_wakeup | 1.090s | 153.923us | 50 | 50 | 100.00 | |
| control_clks | 50 | 50 | 100.00 | |||
| pwrmgr_wakeup | 1.090s | 153.923us | 50 | 50 | 100.00 | |
| aborted_low_power | 100 | 100 | 100.00 | |||
| pwrmgr_aborted_low_power | 1.360s | 88.330us | 50 | 50 | 100.00 | |
| pwrmgr_lowpower_invalid | 1.160s | 43.362us | 50 | 50 | 100.00 | |
| reset | 78 | 100 | 78.00 | |||
| pwrmgr_reset | 2.730s | 1000.000us | 42 | 50 | 84.00 | |
| pwrmgr_reset_invalid | 1.350s | 115.999us | 36 | 50 | 72.00 | |
| main_power_glitch_reset | 42 | 50 | 84.00 | |||
| pwrmgr_reset | 2.730s | 1000.000us | 42 | 50 | 84.00 | |
| reset_wakeup_race | 50 | 50 | 100.00 | |||
| pwrmgr_wakeup_reset | 1.640s | 155.429us | 50 | 50 | 100.00 | |
| lowpower_wakeup_race | 50 | 50 | 100.00 | |||
| pwrmgr_lowpower_wakeup_race | 1.950s | 294.175us | 50 | 50 | 100.00 | |
| disable_rom_integrity_check | 43 | 50 | 86.00 | |||
| pwrmgr_disable_rom_integrity_check | 2.140s | 1000.000us | 43 | 50 | 86.00 | |
| stress_all | 36 | 50 | 72.00 | |||
| pwrmgr_stress_all | 33.720s | 11860.347us | 36 | 50 | 72.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| pwrmgr_intr_test | 1.020s | 17.114us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| pwrmgr_tl_errors | 2.170s | 36.943us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| pwrmgr_tl_errors | 2.170s | 36.943us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| pwrmgr_csr_hw_reset | 1.060s | 27.992us | 5 | 5 | 100.00 | |
| pwrmgr_csr_rw | 1.030s | 21.426us | 20 | 20 | 100.00 | |
| pwrmgr_csr_aliasing | 1.490s | 160.348us | 5 | 5 | 100.00 | |
| pwrmgr_same_csr_outstanding | 1.280s | 108.805us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| pwrmgr_csr_hw_reset | 1.060s | 27.992us | 5 | 5 | 100.00 | |
| pwrmgr_csr_rw | 1.030s | 21.426us | 20 | 20 | 100.00 | |
| pwrmgr_csr_aliasing | 1.490s | 160.348us | 5 | 5 | 100.00 | |
| pwrmgr_same_csr_outstanding | 1.280s | 108.805us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 25 | 25 | 100.00 | |||
| pwrmgr_tl_intg_err | 1.850s | 366.625us | 20 | 20 | 100.00 | |
| pwrmgr_sec_cm | 1.550s | 751.082us | 5 | 5 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| pwrmgr_sec_cm | 1.550s | 751.082us | 5 | 5 | 100.00 | |
| prim_fsm_check | 5 | 5 | 100.00 | |||
| pwrmgr_sec_cm | 1.550s | 751.082us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| pwrmgr_tl_intg_err | 1.850s | 366.625us | 20 | 20 | 100.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 50 | 50 | 100.00 | |||
| pwrmgr_sec_cm_lc_ctrl_intersig_mubi | 3.240s | 975.290us | 50 | 50 | 100.00 | |
| sec_cm_rom_ctrl_intersig_mubi | 50 | 50 | 100.00 | |||
| pwrmgr_wakeup_reset | 1.640s | 155.429us | 50 | 50 | 100.00 | |
| sec_cm_rstmgr_intersig_mubi | 50 | 50 | 100.00 | |||
| pwrmgr_sec_cm_rstmgr_intersig_mubi | 1.430s | 68.123us | 50 | 50 | 100.00 | |
| sec_cm_esc_rx_clk_bkgn_chk | 50 | 50 | 100.00 | |||
| pwrmgr_esc_clk_rst_malfunc | 1.030s | 30.325us | 50 | 50 | 100.00 | |
| sec_cm_esc_rx_clk_local_esc | 5 | 5 | 100.00 | |||
| pwrmgr_sec_cm | 1.550s | 751.082us | 5 | 5 | 100.00 | |
| sec_cm_fsm_sparse | 5 | 5 | 100.00 | |||
| pwrmgr_sec_cm | 1.550s | 751.082us | 5 | 5 | 100.00 | |
| sec_cm_fsm_terminal | 5 | 5 | 100.00 | |||
| pwrmgr_sec_cm | 1.550s | 751.082us | 5 | 5 | 100.00 | |
| sec_cm_ctrl_flow_global_esc | 50 | 50 | 100.00 | |||
| pwrmgr_global_esc | 1.020s | 44.607us | 50 | 50 | 100.00 | |
| sec_cm_main_pd_rst_local_esc | 50 | 50 | 100.00 | |||
| pwrmgr_glitch | 1.010s | 25.347us | 50 | 50 | 100.00 | |
| sec_cm_ctrl_config_regwen | 50 | 50 | 100.00 | |||
| pwrmgr_sec_cm_ctrl_config_regwen | 1.500s | 192.952us | 50 | 50 | 100.00 | |
| sec_cm_wakeup_config_regwen | 20 | 20 | 100.00 | |||
| pwrmgr_csr_rw | 1.030s | 21.426us | 20 | 20 | 100.00 | |
| sec_cm_reset_config_regwen | 20 | 20 | 100.00 | |||
| pwrmgr_csr_rw | 1.030s | 21.426us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| escalation_timeout | 26 | 50 | 52.00 | |||
| pwrmgr_escalation_timeout | 1.310s | 1089.644us | 26 | 50 | 52.00 | |
| stress_all_with_rand_reset | 46 | 50 | 92.00 | |||
| pwrmgr_stress_all_with_rand_reset | 25.250s | 6639.837us | 46 | 50 | 92.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Offending '((!clk_en) || status)' | 24 test runs | |||
| pwrmgr_escalation_timeout | 77857575281037906082350652934599271369668675427972802184506585474784137238556 | 79 |
UVM_ERROR @ 1089643903 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 1089643903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_escalation_timeout | 82903870757055235456065011215180215789003995340389280021024376466380420281289 | 79 |
UVM_ERROR @ 187772075 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 187772075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_escalation_timeout | 27826773959225782902987357272354857213661590965350583452648079704017339002087 | 79 |
UVM_ERROR @ 319358523 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 319358523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_escalation_timeout | 106227994101125871998116151116099833858673355477541920144773003117909196330261 | 79 |
UVM_ERROR @ 99601754 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 99601754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_escalation_timeout | 39455721338091609410051062834275011057849152206142579250002066511344898745684 | 79 |
UVM_ERROR @ 1458307927 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 1458307927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_escalation_timeout | 88476319033078194093951075364008544318589526618156781029052577906711251729467 | 79 |
UVM_ERROR @ 99546038 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 99546038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_escalation_timeout | 113184733864546975324296078538417601790427827069151156409498379193739101993992 | 79 |
UVM_ERROR @ 98536906 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 98536906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_escalation_timeout | 113310398208584327602996414303523868686400729082670805368095595737852213891656 | 79 |
UVM_ERROR @ 101157660 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 101157660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_escalation_timeout | 108647873374417338286747745992032674274179840969616413734976555986390244471583 | 79 |
UVM_ERROR @ 371925743 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 371925743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_escalation_timeout | 33458317699663087750074452165350924399557792193355665189352251272662226037540 | 79 |
UVM_ERROR @ 320252719 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 320252719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_escalation_timeout | 96677763829304172204348631949489118373559280301063359136699539800787477285650 | 79 |
UVM_ERROR @ 100151239 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 100151239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_escalation_timeout | 42840240228162874114261478653472809414780854385534125602543374569137760097804 | 79 |
UVM_ERROR @ 192869836 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 192869836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_escalation_timeout | 4087386074672685863491588038793547919139408736641254189421240543931661546749 | 79 |
UVM_ERROR @ 355309035 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 355309035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_escalation_timeout | 16434740958762312936231750044945288287567860058644417775129711712324578859008 | 79 |
UVM_ERROR @ 100348649 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 100348649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_escalation_timeout | 59096107311002016886522255151753204636841578243856441693221690232971592718068 | 79 |
UVM_ERROR @ 101524695 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 101524695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_escalation_timeout | 73953152752346936010345016602383498512867198423163905961724066662381107592686 | 79 |
UVM_ERROR @ 98883394 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 98883394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_escalation_timeout | 22596366515907248798492715967357925991915676345845388611591193329598930248791 | 79 |
UVM_ERROR @ 344740644 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 344740644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_escalation_timeout | 93110974679228081512693664619936736471430019363000736771836603237357968499365 | 79 |
UVM_ERROR @ 1453173547 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 1453173547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_escalation_timeout | 80697899621542851354338650527914660932303900558775670482678106061817862981062 | 79 |
UVM_ERROR @ 199389253 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 199389253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_escalation_timeout | 88794570302396086336655526285598279498882726284024662456965998558630258592430 | 79 |
UVM_ERROR @ 343043784 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 343043784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_escalation_timeout | 109909688513799984187863833762843596555262256009616217726109407681784592228565 | 79 |
UVM_ERROR @ 1243426204 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 1243426204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_escalation_timeout | 44519790347447143406680528920902126852566693510197219467162050824219447350385 | 79 |
UVM_ERROR @ 99773289 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 99773289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_escalation_timeout | 65673249586314075250687147019058856981651299080370512553175587550322663018401 | 79 |
UVM_ERROR @ 371340609 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 371340609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_escalation_timeout | 638496900857008029943325428980886299182173277187309580521767208912955524684 | 79 |
UVM_ERROR @ 371583268 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 371583268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! | 15 test runs | |||
| pwrmgr_stress_all | 99734880624696730149702495071934066885221979617306788044695650289287207332487 | 902 |
UVM_INFO @ 11295982286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_stress_all | 85724507834212366579968968418148895145688947472862102757868521243394356069285 | 555 |
UVM_INFO @ 13144329247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_stress_all | 107100612333305528453443277720866706772574372051190919983679433456329746668472 | 225 |
UVM_INFO @ 10164946962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_stress_all | 45362782081586746041751431903337273817467832437625840750002978959684529164573 | 368 |
UVM_INFO @ 10378755216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_stress_all | 70588025804885550558463219155365162185105062470228558398517524263396616801902 | 889 |
UVM_INFO @ 12024870169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_stress_all | 100016912543107669540386708066176477163259318607477968621472450005471521704010 | 324 |
UVM_INFO @ 10507640326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_stress_all | 38488583743658027966820366304804196927998803196911629061547529608871364134336 | 621 |
UVM_INFO @ 10743495823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_stress_all | 16388836469638299752415831582134688312956896164073958757467528452740426351265 | 119 |
UVM_INFO @ 10046718950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_stress_all | 330798087784355003047347786114668659889813498816496735391820681260002192442 | 216 |
UVM_INFO @ 10060782218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_stress_all | 103296106440759320607705085943901629950941918980649200178456228230432738117736 | 530 |
UVM_INFO @ 10806362440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_stress_all | 14484115500394155830909478733786788022139041726655887940736263781413779816370 | 1297 |
UVM_INFO @ 13730049240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_stress_all | 93262996424443712949622521497059563404835852499646851184080031803070951801764 | 181 |
UVM_INFO @ 10110776417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_stress_all | 61737323798743377041453548435884930099630371674305980534436242760411658235029 | 1110 |
UVM_INFO @ 11860347447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_stress_all | 23226857435913265796767385296871137910962439534215102054616828942853159732011 | 105 |
UVM_INFO @ 10012217022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_stress_all_with_rand_reset | 90652706807547307159828531695784628705052334769704860339990215525287717425209 | 1436 |
UVM_INFO @ 28553321812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | 15 test runs | |||
| pwrmgr_reset | 108343197728056458525654848275601030844756569679020469647638937153890424090665 | 108 |
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_reset | 39715775786528939418847390658043728588107905276084189573131676024321518138569 | 88 |
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_disable_rom_integrity_check | 68280268924812417243660777496892419138129576797087367024432795284489673048502 | 90 |
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_reset | 50668162243490080307349394211832027537393004902686722754920873213814975968642 | 103 |
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_disable_rom_integrity_check | 52371184266924302767490932452904864968024258238773811276382758628293459427763 | 122 |
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_disable_rom_integrity_check | 54281221530178515028531699159802278787907822497420768832162759394993509632609 | 104 |
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_disable_rom_integrity_check | 59056482786947740826731433710163712163673471949892462814635360798245122109870 | 180 |
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_disable_rom_integrity_check | 53261599421241687695544113051726055422069773169150407036755348488427873680114 | 82 |
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_disable_rom_integrity_check | 111661588905145082467773033151858388760065194671876103518299216969085478879310 | 84 |
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_reset | 44911358383351379283819821989691844066604327367968166031661699212827544457514 | 170 |
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_reset | 22021706954087433343020222985919949183065025634262288764647539349079534434392 | 183 |
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_reset | 100834582841058562638956817285358729688024006464085220783889737635039165043799 | 122 |
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_reset | 94308921216618293997614099753519730061125801811979874769368085056116679851190 | 95 |
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_reset | 87461239178569675985671140185311399057655247089618394142979990907639393461646 | 147 |
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_disable_rom_integrity_check | 97038065429286031807370040862656161903486093481197046616043683214320776841209 | 97 |
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitLowPower | 2 test runs | |||
| pwrmgr_reset_invalid | 59439839683215180070961208019917386700930821306318851703659823890382889057730 | 88 |
UVM_INFO @ 49381991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_reset_invalid | 68752507019730031735682398349064078799294846564437056930279919537662420784365 | 89 |
UVM_INFO @ 52510545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitDisClks | 2 test runs | |||
| pwrmgr_reset_invalid | 51735348795364458213275731644910427032059615119390342530419380116140049765658 | 80 |
UVM_INFO @ 27095139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_reset_invalid | 84350713356773114308686953140130414901461126094451681639338940816479788403994 | 82 |
UVM_INFO @ 28996006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitNvmShutDown | 2 test runs | |||
| pwrmgr_reset_invalid | 73355279793851108400015240452771292135133062177000145852169059822819815047373 | 80 |
UVM_INFO @ 41308317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_reset_invalid | 21979396746420650829161688428905427207880663260419907541701675421664883078727 | 85 |
UVM_INFO @ 34030466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitAckPwrUp | 2 test runs | |||
| pwrmgr_reset_invalid | 49670765965611068070267809242949658379514757506324116957127391597638344254277 | 94 |
UVM_INFO @ 121660410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_reset_invalid | 57089174122320106019773533051710538656702667887732677107710459989017386113869 | 113 |
UVM_INFO @ 91172299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:465) [pwrmgr_common_vseq] wait timeout occurred! | 2 test runs | |||
| pwrmgr_stress_all_with_rand_reset | 44023499607810155824188691479587108593295666128549602225648019035022805981925 | 1587 |
UVM_INFO @ 13955851540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_stress_all_with_rand_reset | 14090535997095387399572997138100469714480935281730652625744570074652649365537 | 1994 |
UVM_INFO @ 13242191104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitReleaseLcRst | 2 test runs | |||
| pwrmgr_reset_invalid | 107088569863576198934016801934728419010605805719342921410101911479029291766454 | 102 |
UVM_INFO @ 66366254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pwrmgr_reset_invalid | 115057978775104926042664146058314702302228071723328538251977818129217383251948 | 103 |
UVM_INFO @ 61830234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitLcInit | 1 test run | |||
| pwrmgr_reset_invalid | 111299615363395400491231954691935733399273240168549425772564919384559173049871 | 104 |
UVM_INFO @ 83457217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitResetPrep | 1 test run | |||
| pwrmgr_reset_invalid | 14991273093060300761187576379928238335622736816873044815352805026267353570541 | 84 |
UVM_INFO @ 44370266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1199) [pwrmgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. | 1 test run | |||
| pwrmgr_stress_all_with_rand_reset | 51758437422521839512149611842747376142814604628936839400828143592474556599095 | 892 |
UVM_INFO @ 1508746273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitRomCheck | 1 test run | |||
| pwrmgr_reset_invalid | 38200810857692002453691103345888366164544228328972495425531042814832970527604 | 92 |
UVM_INFO @ 181325385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitOtpInit | 1 test run | |||
| pwrmgr_reset_invalid | 10678343494384318567086710670606527615391177615877619632445382885289759226332 | 84 |
UVM_INFO @ 146577780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|