Simulation Results: rom_ctrl/32kb

 
23/05/2026 11:52:00 DVSim: v1.49.0 sha: 21f062e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.93 %
  • code
  • 99.68 %
  • assert
  • 97.82 %
  • func
  • 99.28 %
  • line
  • 99.59 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
97.10%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 5.320s 139.052us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 9.000s 174.350us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 7.240s 165.401us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 4.910s 169.047us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 6.910s 1844.463us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.970s 221.347us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 7.240s 165.401us 20 20 100.00
rom_ctrl_csr_aliasing 6.910s 1844.463us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 4.930s 297.379us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 6.120s 167.088us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 5.660s 562.571us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 28.670s 598.924us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 9.800s 4138.977us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 8.210s 542.543us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 10.000s 285.746us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 10.000s 285.746us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 9.000s 174.350us 5 5 100.00
rom_ctrl_csr_rw 7.240s 165.401us 20 20 100.00
rom_ctrl_csr_aliasing 6.910s 1844.463us 5 5 100.00
rom_ctrl_same_csr_outstanding 8.730s 335.942us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 9.000s 174.350us 5 5 100.00
rom_ctrl_csr_rw 7.240s 165.401us 20 20 100.00
rom_ctrl_csr_aliasing 6.910s 1844.463us 5 5 100.00
rom_ctrl_same_csr_outstanding 8.730s 335.942us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 126.580s 8000.783us 18 20 90.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 28.200s 852.564us 20 20 100.00
tl_intg_err 25 25 100.00
rom_ctrl_sec_cm 239.580s 610.295us 5 5 100.00
rom_ctrl_tl_intg_err 72.140s 267.797us 20 20 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 239.580s 610.295us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 239.580s 610.295us 5 5 100.00
sec_cm_checker_ctr_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 126.580s 8000.783us 18 20 90.00
sec_cm_checker_ctrl_flow_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 126.580s 8000.783us 18 20 90.00
sec_cm_checker_fsm_local_esc 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 126.580s 8000.783us 18 20 90.00
sec_cm_compare_ctrl_flow_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 126.580s 8000.783us 18 20 90.00
sec_cm_compare_ctr_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 126.580s 8000.783us 18 20 90.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 239.580s 610.295us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 239.580s 610.295us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 5.320s 139.052us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 5.320s 139.052us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 5.320s 139.052us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 72.140s 267.797us 20 20 100.00
sec_cm_bus_local_esc 20 22 90.91
rom_ctrl_corrupt_sig_fatal_chk 126.580s 8000.783us 18 20 90.00
rom_ctrl_kmac_err_chk 9.800s 4138.977us 2 2 100.00
sec_cm_mux_mubi 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 126.580s 8000.783us 18 20 90.00
sec_cm_mux_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 126.580s 8000.783us 18 20 90.00
sec_cm_ctrl_redun 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 126.580s 8000.783us 18 20 90.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 28.200s 852.564us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 239.580s 610.295us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 18 20 90.00
rom_ctrl_stress_all_with_rand_reset 497.820s 19266.847us 18 20 90.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) 2 test runs
rom_ctrl_corrupt_sig_fatal_chk 54664353174135105819350168981162161383859148226261132851269514441135997459672 96
UVM_INFO @ 518788069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 106362452177494480934267549027291967832454510062695517408827466678505870690357 78
UVM_INFO @ 368372252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:235) [scoreboard] Check failed item.d_data[i**+:*] == exp_data[i**+:*] (* [*] vs * [*]) TLUL ROM read data incorrect 2 test runs
rom_ctrl_stress_all_with_rand_reset 24967929989121525120362241193717464609767956930852571588605198127308391373308 131
UVM_INFO @ 4291976953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 89679835546227502854391272555758574406072554142114036243611534843105477315892 154
UVM_INFO @ 7448884333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---