Simulation Results: rom_ctrl/64kb

 
23/05/2026 11:52:00 DVSim: v1.49.0 sha: 21f062e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.88 %
  • code
  • 99.68 %
  • assert
  • 97.67 %
  • func
  • 99.28 %
  • line
  • 99.59 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 9.570s 221.721us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 14.890s 291.696us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 11.440s 291.691us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 12.310s 1069.824us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 17.250s 4319.161us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 17.880s 4044.906us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 11.440s 291.691us 20 20 100.00
rom_ctrl_csr_aliasing 17.250s 4319.161us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 11.550s 556.123us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 11.390s 287.108us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 9.600s 307.603us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 63.300s 4077.563us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 27.720s 2102.685us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 14.350s 2084.323us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 22.900s 1071.216us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 22.900s 1071.216us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 14.890s 291.696us 5 5 100.00
rom_ctrl_csr_rw 11.440s 291.691us 20 20 100.00
rom_ctrl_csr_aliasing 17.250s 4319.161us 5 5 100.00
rom_ctrl_same_csr_outstanding 13.540s 1610.634us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 14.890s 291.696us 5 5 100.00
rom_ctrl_csr_rw 11.440s 291.691us 20 20 100.00
rom_ctrl_csr_aliasing 17.250s 4319.161us 5 5 100.00
rom_ctrl_same_csr_outstanding 13.540s 1610.634us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 206.650s 5246.717us 20 20 100.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 62.010s 4383.919us 20 20 100.00
tl_intg_err 25 25 100.00
rom_ctrl_sec_cm 606.020s 3481.814us 5 5 100.00
rom_ctrl_tl_intg_err 135.430s 9365.712us 20 20 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 606.020s 3481.814us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 606.020s 3481.814us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 206.650s 5246.717us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 206.650s 5246.717us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 206.650s 5246.717us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 206.650s 5246.717us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 206.650s 5246.717us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 606.020s 3481.814us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 606.020s 3481.814us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 9.570s 221.721us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 9.570s 221.721us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 9.570s 221.721us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 135.430s 9365.712us 20 20 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 206.650s 5246.717us 20 20 100.00
rom_ctrl_kmac_err_chk 27.720s 2102.685us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 206.650s 5246.717us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 206.650s 5246.717us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 206.650s 5246.717us 20 20 100.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 62.010s 4383.919us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 606.020s 3481.814us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 311.570s 4310.418us 20 20 100.00