Simulation Results: rstmgr

 
23/05/2026 11:52:00 DVSim: v1.49.0 sha: 21f062e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 99.12 %
  • code
  • 99.68 %
  • assert
  • 98.93 %
  • func
  • 98.76 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 99.38 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
rstmgr_smoke 2.230s 254.453us 50 50 100.00
csr_hw_reset 5 5 100.00
rstmgr_csr_hw_reset 1.250s 108.125us 5 5 100.00
csr_rw 20 20 100.00
rstmgr_csr_rw 1.260s 93.451us 20 20 100.00
csr_bit_bash 5 5 100.00
rstmgr_csr_bit_bash 9.320s 2268.427us 5 5 100.00
csr_aliasing 5 5 100.00
rstmgr_csr_aliasing 2.890s 415.778us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.940s 182.067us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rstmgr_csr_rw 1.260s 93.451us 20 20 100.00
rstmgr_csr_aliasing 2.890s 415.778us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 50 50 100.00
rstmgr_por_stretcher 1.420s 211.274us 50 50 100.00
sw_rst 50 50 100.00
rstmgr_sw_rst 3.620s 549.165us 50 50 100.00
sw_rst_reset_race 50 50 100.00
rstmgr_sw_rst_reset_race 2.260s 324.115us 50 50 100.00
reset_info 50 50 100.00
rstmgr_reset 7.740s 1868.300us 50 50 100.00
cpu_info 50 50 100.00
rstmgr_reset 7.740s 1868.300us 50 50 100.00
alert_info 50 50 100.00
rstmgr_reset 7.740s 1868.300us 50 50 100.00
reset_info_capture 50 50 100.00
rstmgr_reset 7.740s 1868.300us 50 50 100.00
stress_all 50 50 100.00
rstmgr_stress_all 63.470s 15348.154us 50 50 100.00
alert_test 50 50 100.00
rstmgr_alert_test 1.240s 74.573us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rstmgr_tl_errors 3.440s 410.454us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rstmgr_tl_errors 3.440s 410.454us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rstmgr_csr_hw_reset 1.250s 108.125us 5 5 100.00
rstmgr_csr_rw 1.260s 93.451us 20 20 100.00
rstmgr_csr_aliasing 2.890s 415.778us 5 5 100.00
rstmgr_same_csr_outstanding 2.070s 252.663us 20 20 100.00
tl_d_partial_access 50 50 100.00
rstmgr_csr_hw_reset 1.250s 108.125us 5 5 100.00
rstmgr_csr_rw 1.260s 93.451us 20 20 100.00
rstmgr_csr_aliasing 2.890s 415.778us 5 5 100.00
rstmgr_same_csr_outstanding 2.070s 252.663us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
rstmgr_sec_cm 26.990s 16834.132us 5 5 100.00
rstmgr_tl_intg_err 3.870s 879.489us 20 20 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 26.990s 16834.132us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 26.990s 16834.132us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
rstmgr_tl_intg_err 3.870s 879.489us 20 20 100.00
sec_cm_scan_intersig_mubi 50 50 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.830s 199.120us 50 50 100.00
sec_cm_leaf_rst_bkgn_chk 50 50 100.00
rstmgr_leaf_rst_cnsty 9.560s 2679.516us 50 50 100.00
sec_cm_leaf_rst_shadow 50 50 100.00
rstmgr_leaf_rst_shadow_attack 1.900s 303.234us 50 50 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 26.990s 16834.132us 5 5 100.00
sec_cm_sw_rst_config_regwen 20 20 100.00
rstmgr_csr_rw 1.260s 93.451us 20 20 100.00
sec_cm_dump_ctrl_config_regwen 20 20 100.00
rstmgr_csr_rw 1.260s 93.451us 20 20 100.00