Simulation Results: rv_timer

 
23/05/2026 11:52:00 DVSim: v1.49.0 sha: 21f062e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 99.58 %
  • code
  • 100.00 %
  • assert
  • 98.73 %
  • func
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
92.50%
V2S
100.00%
V3
42.50%
Testpoint Test Max Runtime Sim Time Pass Total %
random 20 20 100.00
rv_timer_random 2.220s 1069.288us 20 20 100.00
csr_hw_reset 5 5 100.00
rv_timer_csr_hw_reset 0.780s 20.454us 5 5 100.00
csr_rw 20 20 100.00
rv_timer_csr_rw 0.880s 16.266us 20 20 100.00
csr_bit_bash 5 5 100.00
rv_timer_csr_bit_bash 4.110s 1700.944us 5 5 100.00
csr_aliasing 5 5 100.00
rv_timer_csr_aliasing 0.990s 38.489us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.260s 59.175us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rv_timer_csr_rw 0.880s 16.266us 20 20 100.00
rv_timer_csr_aliasing 0.990s 38.489us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 2 20 10.00
rv_timer_random_reset 2.870s 2097.031us 2 20 10.00
disabled 20 20 100.00
rv_timer_disabled 3.030s 2461.430us 20 20 100.00
cfg_update_on_fly 10 10 100.00
rv_timer_cfg_update_on_fly 642.990s 1436469.594us 10 10 100.00
no_interrupt_test 10 10 100.00
rv_timer_cfg_update_on_fly 642.990s 1436469.594us 10 10 100.00
stress 20 20 100.00
rv_timer_stress_all 9.530s 13094.589us 20 20 100.00
alert_test 50 50 100.00
rv_timer_alert_test 0.910s 11.792us 50 50 100.00
intr_test 50 50 100.00
rv_timer_intr_test 0.820s 25.950us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rv_timer_tl_errors 2.580s 221.176us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rv_timer_tl_errors 2.580s 221.176us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rv_timer_csr_hw_reset 0.780s 20.454us 5 5 100.00
rv_timer_csr_rw 0.880s 16.266us 20 20 100.00
rv_timer_csr_aliasing 0.990s 38.489us 5 5 100.00
rv_timer_same_csr_outstanding 0.930s 22.993us 20 20 100.00
tl_d_partial_access 50 50 100.00
rv_timer_csr_hw_reset 0.780s 20.454us 5 5 100.00
rv_timer_csr_rw 0.880s 16.266us 20 20 100.00
rv_timer_csr_aliasing 0.990s 38.489us 5 5 100.00
rv_timer_same_csr_outstanding 0.930s 22.993us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
rv_timer_sec_cm 1.100s 216.392us 5 5 100.00
rv_timer_tl_intg_err 1.480s 504.843us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
rv_timer_tl_intg_err 1.480s 504.843us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 2 10 20.00
rv_timer_min 1.860s 325.580us 2 10 20.00
max_value 1 10 10.00
rv_timer_max 1.060s 787.833us 1 10 10.00
stress_all_with_rand_reset 14 20 70.00
rv_timer_stress_all_with_rand_reset 50.190s 5493.098us 14 20 70.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 26 test runs
rv_timer_random_reset 109931345448495204907427657189491272932288041801746231642352359502792665202083 77
UVM_INFO @ 146679246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 53643118373474659479052407474529481140830785901808045188995882490443594201625 75
UVM_INFO @ 225351153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 111430371956005816142619292678994600487427961684227250612898078970479064154412 75
UVM_INFO @ 239240213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 49709032172526229811529127592317811212026739728594810431255789384891638508346 75
UVM_INFO @ 120922792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 76071848810348711573623575787395205095092362070077587327483570661360778032713 75
UVM_INFO @ 1096322033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 11980889193461394565695730367872804071254589946723780200054407026508746666571 76
UVM_INFO @ 120413491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 59454994876764342250905937531106615784918271541719816674822812339581575196877 75
UVM_INFO @ 163877088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 53119421708571276922375920931058526422201351244279506825826396150080977171651 77
UVM_INFO @ 227615953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 51358546238921421744062227227144805729991218416829796431175942812247666501060 75
UVM_INFO @ 576191626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 14950481209427041825133212886083207114524451647275068008634303721587793555641 78
UVM_INFO @ 325579706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 51542417073240959450585828573861372696876079686289989772689694415426734723234 76
UVM_INFO @ 1804174352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 98318100667185869193373194380238750754802684486189800153629473510118549512279 76
UVM_INFO @ 66601476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 81833605924996564838827477353100495310040932778000164437430964718243511980536 75
UVM_INFO @ 308058927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 111881578712212244231962145475433869813260703916992905324524368904751024471678 77
UVM_INFO @ 137425421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 100574973037577837154396298501915179176144033232029255750113544334641722526238 75
UVM_INFO @ 125621280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 18443904426639351230663100077615063361831358622817818378863700991021650492502 75
UVM_INFO @ 96657652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 13952859843642818062284342748229373834200121004394965604090682772384936350735 75
UVM_INFO @ 614905938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 69501691981869486524445786622403555203290577584100443080051087671704529519824 75
UVM_INFO @ 84868248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 2666361362318009235738441814259929460949768256880645195542826120597386651429 75
UVM_INFO @ 2097031281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 74343511513343007459630280598614399077477378470676907176858246533253098787082 75
UVM_INFO @ 315693302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 67102411377058120386813482135765870966321668377785722048956262709981379484361 75
UVM_INFO @ 783126501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 90473982387022882084903441449045085466390396596486661476359020158102205320344 75
UVM_INFO @ 603179010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 114793393409787017591900798194711616635497693970565258391637085106531735100641 76
UVM_INFO @ 569631794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 28668158238150895218367656294950743276783761926232853631701999971862699874426 75
UVM_INFO @ 1960211124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 80832095070823996792829018230576209188352822560860984594841467086891984566501 75
UVM_INFO @ 1236956771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 52980815027363392198562710455312875942760418505340175105161781070181131948215 75
UVM_INFO @ 625306826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 9 test runs
rv_timer_max 7601488101862548837964617444950327540126437782127835838443245598118055056780 75
UVM_INFO @ 284281479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 31370482945191705419937417113659233393186416905482702658512020378083455173253 75
UVM_INFO @ 787833189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 87624081149407687814625093739441164016569098855082297041774410535939422703591 75
UVM_INFO @ 173715071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 18983000535709936085512845620443015437190745974553130362848324010629738252134 75
UVM_INFO @ 117158688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 35540676458806592797972398023712957808385711055038365450245282513065556683030 75
UVM_INFO @ 45938536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 63755425500260892015694219270057408089799224678277666130938187174588427147842 75
UVM_INFO @ 44281022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 43957953320947400672898540762361346628997729254713148206251620713069282944430 75
UVM_INFO @ 54206815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 31856872867549560338960259457266989888209539898150189137287484135506437811102 75
UVM_INFO @ 427718130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 84858404326183114177745008390064155417599028351594823725797188650029287505227 75
UVM_INFO @ 45736872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) 4 test runs
rv_timer_stress_all_with_rand_reset 96424439441566826335785547769542587825668161767688645468124736745885413232725 103
UVM_INFO @ 12432999699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 98568408420311218782460670813616530459426519044067067616150209173715591816530 416
UVM_INFO @ 5493097879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 107613868354893339110206095194603757226187558256478115420639068066103636870953 314
UVM_INFO @ 13588866442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 89807070508858885930660021460062538392912889543893006963924302846315749268267 224
UVM_INFO @ 3153509388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
rv_timer_stress_all_with_rand_reset 99579149170681894517551169846932038133897182731210498781660865032214699745152 371
UVM_INFO @ 4121360909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 88770219945345715030875242119368911706307609632168206346519751062983560903702 346
UVM_INFO @ 1964172149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---