Simulation Results: spi_device/2p

 
23/05/2026 11:52:00 DVSim: v1.49.0 sha: 21f062e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.32 %
  • code
  • 94.22 %
  • assert
  • 95.49 %
  • func
  • 99.26 %
  • line
  • 98.96 %
  • branch
  • 98.39 %
  • cond
  • 96.63 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
99.90%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
spi_device_flash_and_tpm 576.420s 308758.970us 50 50 100.00
csr_hw_reset 5 5 100.00
spi_device_csr_hw_reset 1.870s 189.653us 5 5 100.00
csr_rw 20 20 100.00
spi_device_csr_rw 3.090s 436.265us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_device_csr_bit_bash 37.130s 11046.601us 5 5 100.00
csr_aliasing 5 5 100.00
spi_device_csr_aliasing 20.270s 2443.815us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_device_csr_mem_rw_with_rand_reset 4.510s 584.909us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_device_csr_rw 3.090s 436.265us 20 20 100.00
spi_device_csr_aliasing 20.270s 2443.815us 5 5 100.00
mem_walk 5 5 100.00
spi_device_mem_walk 1.070s 13.576us 5 5 100.00
mem_partial_access 5 5 100.00
spi_device_mem_partial_access 2.200s 196.519us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 50 50 100.00
spi_device_csb_read 1.210s 65.427us 50 50 100.00
mem_parity 20 20 100.00
spi_device_mem_parity 1.540s 126.676us 20 20 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 1.150s 16.217us 1 1 100.00
tpm_read 50 50 100.00
spi_device_tpm_rw 7.560s 357.202us 50 50 100.00
tpm_write 50 50 100.00
spi_device_tpm_rw 7.560s 357.202us 50 50 100.00
tpm_hw_reg 100 100 100.00
spi_device_tpm_read_hw_reg 28.340s 37138.921us 50 50 100.00
spi_device_tpm_sts_read 1.530s 362.946us 50 50 100.00
tpm_fully_random_case 50 50 100.00
spi_device_tpm_all 41.610s 29200.693us 50 50 100.00
pass_cmd_filtering 100 100 100.00
spi_device_pass_cmd_filtering 25.120s 4979.167us 50 50 100.00
spi_device_flash_all 218.620s 250949.757us 50 50 100.00
pass_addr_translation 100 100 100.00
spi_device_pass_addr_payload_swap 41.930s 63963.232us 50 50 100.00
spi_device_flash_all 218.620s 250949.757us 50 50 100.00
pass_payload_translation 100 100 100.00
spi_device_pass_addr_payload_swap 41.930s 63963.232us 50 50 100.00
spi_device_flash_all 218.620s 250949.757us 50 50 100.00
cmd_info_slots 50 50 100.00
spi_device_flash_all 218.620s 250949.757us 50 50 100.00
cmd_read_status 100 100 100.00
spi_device_intercept 21.350s 10194.142us 50 50 100.00
spi_device_flash_all 218.620s 250949.757us 50 50 100.00
cmd_read_jedec 100 100 100.00
spi_device_intercept 21.350s 10194.142us 50 50 100.00
spi_device_flash_all 218.620s 250949.757us 50 50 100.00
cmd_read_sfdp 100 100 100.00
spi_device_intercept 21.350s 10194.142us 50 50 100.00
spi_device_flash_all 218.620s 250949.757us 50 50 100.00
cmd_fast_read 100 100 100.00
spi_device_intercept 21.350s 10194.142us 50 50 100.00
spi_device_flash_all 218.620s 250949.757us 50 50 100.00
cmd_read_pipeline 100 100 100.00
spi_device_intercept 21.350s 10194.142us 50 50 100.00
spi_device_flash_all 218.620s 250949.757us 50 50 100.00
flash_cmd_upload 50 50 100.00
spi_device_upload 34.790s 10425.085us 50 50 100.00
mailbox_command 50 50 100.00
spi_device_mailbox 117.470s 75608.658us 50 50 100.00
mailbox_cross_outside_command 50 50 100.00
spi_device_mailbox 117.470s 75608.658us 50 50 100.00
mailbox_cross_inside_command 50 50 100.00
spi_device_mailbox 117.470s 75608.658us 50 50 100.00
cmd_read_buffer 100 100 100.00
spi_device_flash_mode 31.280s 8352.155us 50 50 100.00
spi_device_read_buffer_direct 16.280s 3444.009us 50 50 100.00
cmd_dummy_cycle 100 100 100.00
spi_device_mailbox 117.470s 75608.658us 50 50 100.00
spi_device_flash_all 218.620s 250949.757us 50 50 100.00
quad_spi 50 50 100.00
spi_device_flash_all 218.620s 250949.757us 50 50 100.00
dual_spi 50 50 100.00
spi_device_flash_all 218.620s 250949.757us 50 50 100.00
4b_3b_feature 50 50 100.00
spi_device_cfg_cmd 21.740s 14804.640us 50 50 100.00
write_enable_disable 50 50 100.00
spi_device_cfg_cmd 21.740s 14804.640us 50 50 100.00
TPM_with_flash_or_passthrough_mode 50 50 100.00
spi_device_flash_and_tpm 576.420s 308758.970us 50 50 100.00
tpm_and_flash_trans_with_min_inactive_time 49 50 98.00
spi_device_flash_and_tpm_min_idle 3600.116s 0.000us 49 50 98.00
stress_all 50 50 100.00
spi_device_stress_all 708.940s 118855.464us 50 50 100.00
alert_test 50 50 100.00
spi_device_alert_test 1.160s 140.069us 50 50 100.00
intr_test 50 50 100.00
spi_device_intr_test 1.200s 55.114us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_device_tl_errors 5.990s 254.200us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_device_tl_errors 5.990s 254.200us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_device_csr_hw_reset 1.870s 189.653us 5 5 100.00
spi_device_csr_rw 3.090s 436.265us 20 20 100.00
spi_device_csr_aliasing 20.270s 2443.815us 5 5 100.00
spi_device_same_csr_outstanding 5.180s 224.459us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_device_csr_hw_reset 1.870s 189.653us 5 5 100.00
spi_device_csr_rw 3.090s 436.265us 20 20 100.00
spi_device_csr_aliasing 20.270s 2443.815us 5 5 100.00
spi_device_same_csr_outstanding 5.180s 224.459us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_device_sec_cm 1.710s 305.435us 5 5 100.00
spi_device_tl_intg_err 21.090s 1753.105us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
spi_device_tl_intg_err 21.090s 1753.105us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 50 50 100.00
spi_device_flash_mode_ignore_cmds 275.330s 49791.800us 50 50 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 1 test run
spi_device_flash_and_tpm_min_idle 68308261192079453323841710637212093137147541005979535051604915245259738943765 None