Simulation Results: spi_host

 
23/05/2026 11:52:00 DVSim: v1.49.0 sha: 21f062e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.19 %
  • code
  • 95.03 %
  • assert
  • 96.78 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.87%
V2S
100.00%
unmapped
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
spi_host_smoke 104.000s 2730.420us 50 50 100.00
csr_hw_reset 5 5 100.00
spi_host_csr_hw_reset 2.000s 30.714us 5 5 100.00
csr_rw 20 20 100.00
spi_host_csr_rw 2.000s 30.297us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_host_csr_bit_bash 4.000s 268.371us 5 5 100.00
csr_aliasing 5 5 100.00
spi_host_csr_aliasing 2.000s 27.804us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 32.736us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_host_csr_rw 2.000s 30.297us 20 20 100.00
spi_host_csr_aliasing 2.000s 27.804us 5 5 100.00
mem_walk 5 5 100.00
spi_host_mem_walk 2.000s 16.916us 5 5 100.00
mem_partial_access 5 5 100.00
spi_host_mem_partial_access 2.000s 54.066us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 50 50 100.00
spi_host_performance 2.000s 24.326us 50 50 100.00
error_event_intr 150 150 100.00
spi_host_overflow_underflow 44.000s 3192.336us 50 50 100.00
spi_host_error_cmd 2.000s 24.344us 50 50 100.00
spi_host_event 414.000s 31816.119us 50 50 100.00
clock_rate 50 50 100.00
spi_host_speed 7.000s 392.101us 50 50 100.00
speed 50 50 100.00
spi_host_speed 7.000s 392.101us 50 50 100.00
chip_select_timing 50 50 100.00
spi_host_speed 7.000s 392.101us 50 50 100.00
sw_reset 50 50 100.00
spi_host_sw_reset 57.000s 3209.321us 50 50 100.00
passthrough_mode 50 50 100.00
spi_host_passthrough_mode 2.000s 38.080us 50 50 100.00
cpol_cpha 50 50 100.00
spi_host_speed 7.000s 392.101us 50 50 100.00
full_cycle 50 50 100.00
spi_host_speed 7.000s 392.101us 50 50 100.00
duplex 50 50 100.00
spi_host_smoke 104.000s 2730.420us 50 50 100.00
tx_rx_only 50 50 100.00
spi_host_smoke 104.000s 2730.420us 50 50 100.00
stress_all 49 50 98.00
spi_host_stress_all 1810.000s 1000000.000us 49 50 98.00
spien 50 50 100.00
spi_host_spien 150.000s 14223.499us 50 50 100.00
stall 50 50 100.00
spi_host_status_stall 788.000s 85258.622us 50 50 100.00
Idlecsbactive 50 50 100.00
spi_host_idlecsbactive 30.000s 9006.204us 50 50 100.00
data_fifo_status 50 50 100.00
spi_host_overflow_underflow 44.000s 3192.336us 50 50 100.00
alert_test 50 50 100.00
spi_host_alert_test 2.000s 26.382us 50 50 100.00
intr_test 50 50 100.00
spi_host_intr_test 2.000s 54.741us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_host_tl_errors 4.000s 533.510us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_host_tl_errors 4.000s 533.510us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 30.714us 5 5 100.00
spi_host_csr_rw 2.000s 30.297us 20 20 100.00
spi_host_csr_aliasing 2.000s 27.804us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 50.534us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 30.714us 5 5 100.00
spi_host_csr_rw 2.000s 30.297us 20 20 100.00
spi_host_csr_aliasing 2.000s 27.804us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 50.534us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_host_tl_intg_err 2.000s 101.859us 20 20 100.00
spi_host_sec_cm 2.000s 286.503us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
spi_host_tl_intg_err 2.000s 101.859us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 9 10 90.00
spi_host_upper_range_clkdiv 621.000s 50613.980us 9 10 90.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 2 test runs
spi_host_upper_range_clkdiv 80721821281613779590038224469761311470270807465040172359433631388530057511619 115
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_stress_all 74576864999162401585599304514664260997060975954028945129577901836721374657389 177
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---