| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 5 | 5 | 100.00 | |||
| sram_ctrl_smoke | 8.000s | 1313.212us | 5 | 5 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 2.000s | 14.454us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 11.392us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_bit_bash | 3.000s | 414.727us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_aliasing | 2.000s | 51.381us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 6.000s | 4938.211us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 11.392us | 20 | 20 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 51.381us | 5 | 5 | 100.00 | |
| mem_walk | 5 | 5 | 100.00 | |||
| sram_ctrl_mem_walk | 252.000s | 21198.029us | 5 | 5 | 100.00 | |
| mem_partial_access | 5 | 5 | 100.00 | |||
| sram_ctrl_mem_partial_access | 117.000s | 22892.061us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| multiple_keys | 5 | 5 | 100.00 | |||
| sram_ctrl_multiple_keys | 56.000s | 7031.879us | 5 | 5 | 100.00 | |
| stress_pipeline | 5 | 5 | 100.00 | |||
| sram_ctrl_stress_pipeline | 220.000s | 6045.515us | 5 | 5 | 100.00 | |
| bijection | 5 | 5 | 100.00 | |||
| sram_ctrl_bijection | 208.000s | 17079.823us | 5 | 5 | 100.00 | |
| access_during_key_req | 5 | 5 | 100.00 | |||
| sram_ctrl_access_during_key_req | 69.000s | 49811.417us | 5 | 5 | 100.00 | |
| lc_escalation | 5 | 5 | 100.00 | |||
| sram_ctrl_lc_escalation | 44.000s | 57732.225us | 5 | 5 | 100.00 | |
| executable | 5 | 5 | 100.00 | |||
| sram_ctrl_executable | 49.000s | 108470.276us | 5 | 5 | 100.00 | |
| partial_access | 10 | 10 | 100.00 | |||
| sram_ctrl_partial_access | 9.000s | 715.246us | 5 | 5 | 100.00 | |
| sram_ctrl_partial_access_b2b | 350.000s | 47492.863us | 5 | 5 | 100.00 | |
| max_throughput | 15 | 15 | 100.00 | |||
| sram_ctrl_max_throughput | 9.000s | 4450.989us | 5 | 5 | 100.00 | |
| sram_ctrl_throughput_w_partial_write | 7.000s | 832.510us | 5 | 5 | 100.00 | |
| sram_ctrl_throughput_w_readback | 7.000s | 1360.791us | 5 | 5 | 100.00 | |
| regwen | 5 | 5 | 100.00 | |||
| sram_ctrl_regwen | 22.000s | 2969.566us | 5 | 5 | 100.00 | |
| ram_cfg | 5 | 5 | 100.00 | |||
| sram_ctrl_ram_cfg | 4.000s | 1350.454us | 5 | 5 | 100.00 | |
| stress_all | 5 | 5 | 100.00 | |||
| sram_ctrl_stress_all | 237.000s | 73387.508us | 5 | 5 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| sram_ctrl_alert_test | 2.000s | 21.051us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| sram_ctrl_tl_errors | 6.000s | 608.948us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| sram_ctrl_tl_errors | 6.000s | 608.948us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 2.000s | 14.454us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 11.392us | 20 | 20 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 51.381us | 5 | 5 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 24.921us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 2.000s | 14.454us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 11.392us | 20 | 20 | 100.00 | |
| sram_ctrl_csr_aliasing | 2.000s | 51.381us | 5 | 5 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 24.921us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| passthru_mem_tl_intg_err | 20 | 20 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 46.000s | 28206.967us | 20 | 20 | 100.00 | |
| tl_intg_err | 25 | 25 | 100.00 | |||
| sram_ctrl_sec_cm | 7.000s | 1500.308us | 5 | 5 | 100.00 | |
| sram_ctrl_tl_intg_err | 4.000s | 213.340us | 20 | 20 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 7.000s | 1500.308us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| sram_ctrl_tl_intg_err | 4.000s | 213.340us | 20 | 20 | 100.00 | |
| sec_cm_ctrl_config_regwen | 5 | 5 | 100.00 | |||
| sram_ctrl_regwen | 22.000s | 2969.566us | 5 | 5 | 100.00 | |
| sec_cm_readback_config_regwen | 5 | 5 | 100.00 | |||
| sram_ctrl_regwen | 22.000s | 2969.566us | 5 | 5 | 100.00 | |
| sec_cm_exec_config_regwen | 20 | 20 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 11.392us | 20 | 20 | 100.00 | |
| sec_cm_exec_config_mubi | 5 | 5 | 100.00 | |||
| sram_ctrl_executable | 49.000s | 108470.276us | 5 | 5 | 100.00 | |
| sec_cm_exec_intersig_mubi | 5 | 5 | 100.00 | |||
| sram_ctrl_executable | 49.000s | 108470.276us | 5 | 5 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 5 | 5 | 100.00 | |||
| sram_ctrl_executable | 49.000s | 108470.276us | 5 | 5 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 5 | 5 | 100.00 | |||
| sram_ctrl_lc_escalation | 44.000s | 57732.225us | 5 | 5 | 100.00 | |
| sec_cm_prim_ram_ctrl_mubi | 5 | 5 | 100.00 | |||
| sram_ctrl_mubi_enc_err | 9.000s | 1432.519us | 5 | 5 | 100.00 | |
| sec_cm_mem_integrity | 20 | 20 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 46.000s | 28206.967us | 20 | 20 | 100.00 | |
| sec_cm_mem_readback | 5 | 5 | 100.00 | |||
| sram_ctrl_readback_err | 8.000s | 5526.015us | 5 | 5 | 100.00 | |
| sec_cm_mem_scramble | 5 | 5 | 100.00 | |||
| sram_ctrl_smoke | 8.000s | 1313.212us | 5 | 5 | 100.00 | |
| sec_cm_addr_scramble | 5 | 5 | 100.00 | |||
| sram_ctrl_smoke | 8.000s | 1313.212us | 5 | 5 | 100.00 | |
| sec_cm_instr_bus_lc_gated | 5 | 5 | 100.00 | |||
| sram_ctrl_executable | 49.000s | 108470.276us | 5 | 5 | 100.00 | |
| sec_cm_ram_tl_lc_gate_fsm_sparse | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 7.000s | 1500.308us | 5 | 5 | 100.00 | |
| sec_cm_key_global_esc | 5 | 5 | 100.00 | |||
| sram_ctrl_lc_escalation | 44.000s | 57732.225us | 5 | 5 | 100.00 | |
| sec_cm_key_local_esc | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 7.000s | 1500.308us | 5 | 5 | 100.00 | |
| sec_cm_init_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 7.000s | 1500.308us | 5 | 5 | 100.00 | |
| sec_cm_scramble_key_sideload | 5 | 5 | 100.00 | |||
| sram_ctrl_smoke | 8.000s | 1313.212us | 5 | 5 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 7.000s | 1500.308us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 5 | 5 | 100.00 | |||
| sram_ctrl_stress_all_with_rand_reset | 38.000s | 4564.549us | 5 | 5 | 100.00 | |