Simulation Results: sram_ctrl/ret

 
23/05/2026 11:52:00 DVSim: v1.49.0 sha: 21f062e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.77 %
  • code
  • 83.42 %
  • assert
  • 98.08 %
  • func
  • 96.80 %
  • block
  • 93.87 %
  • line
  • 95.04 %
  • branch
  • 89.67 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
98.57%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
sram_ctrl_smoke 2.000s 74.949us 5 5 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 2.000s 28.495us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 2.000s 35.801us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 3.000s 47.106us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 64.509us 5 5 100.00
csr_mem_rw_with_rand_reset 19 20 95.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 41.334us 19 20 95.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 2.000s 35.801us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 64.509us 5 5 100.00
mem_walk 5 5 100.00
sram_ctrl_mem_walk 14.000s 2188.627us 5 5 100.00
mem_partial_access 5 5 100.00
sram_ctrl_mem_partial_access 7.000s 773.839us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 5 5 100.00
sram_ctrl_multiple_keys 12.000s 1833.739us 5 5 100.00
stress_pipeline 5 5 100.00
sram_ctrl_stress_pipeline 205.000s 3774.386us 5 5 100.00
bijection 5 5 100.00
sram_ctrl_bijection 10.000s 1981.169us 5 5 100.00
access_during_key_req 5 5 100.00
sram_ctrl_access_during_key_req 33.000s 15120.487us 5 5 100.00
lc_escalation 5 5 100.00
sram_ctrl_lc_escalation 11.000s 2804.231us 5 5 100.00
executable 5 5 100.00
sram_ctrl_executable 17.000s 2262.990us 5 5 100.00
partial_access 10 10 100.00
sram_ctrl_partial_access 2.000s 142.323us 5 5 100.00
sram_ctrl_partial_access_b2b 285.000s 17189.019us 5 5 100.00
max_throughput 15 15 100.00
sram_ctrl_max_throughput 2.000s 91.095us 5 5 100.00
sram_ctrl_throughput_w_partial_write 2.000s 70.145us 5 5 100.00
sram_ctrl_throughput_w_readback 2.000s 72.494us 5 5 100.00
regwen 5 5 100.00
sram_ctrl_regwen 10.000s 3624.200us 5 5 100.00
ram_cfg 5 5 100.00
sram_ctrl_ram_cfg 2.000s 28.079us 5 5 100.00
stress_all 5 5 100.00
sram_ctrl_stress_all 56.000s 9083.585us 5 5 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 2.000s 53.169us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 6.000s 198.586us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 6.000s 198.586us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 28.495us 5 5 100.00
sram_ctrl_csr_rw 2.000s 35.801us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 64.509us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 34.227us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 28.495us 5 5 100.00
sram_ctrl_csr_rw 2.000s 35.801us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 64.509us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 34.227us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 6.000s 3622.412us 20 20 100.00
tl_intg_err 25 25 100.00
sram_ctrl_sec_cm 5.000s 2691.387us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 193.971us 20 20 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 2691.387us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 4.000s 193.971us 20 20 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
sram_ctrl_regwen 10.000s 3624.200us 5 5 100.00
sec_cm_readback_config_regwen 5 5 100.00
sram_ctrl_regwen 10.000s 3624.200us 5 5 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 2.000s 35.801us 20 20 100.00
sec_cm_exec_config_mubi 5 5 100.00
sram_ctrl_executable 17.000s 2262.990us 5 5 100.00
sec_cm_exec_intersig_mubi 5 5 100.00
sram_ctrl_executable 17.000s 2262.990us 5 5 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 5 5 100.00
sram_ctrl_executable 17.000s 2262.990us 5 5 100.00
sec_cm_lc_escalate_en_intersig_mubi 5 5 100.00
sram_ctrl_lc_escalation 11.000s 2804.231us 5 5 100.00
sec_cm_prim_ram_ctrl_mubi 5 5 100.00
sram_ctrl_mubi_enc_err 2.000s 40.939us 5 5 100.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 6.000s 3622.412us 20 20 100.00
sec_cm_mem_readback 5 5 100.00
sram_ctrl_readback_err 2.000s 40.156us 5 5 100.00
sec_cm_mem_scramble 5 5 100.00
sram_ctrl_smoke 2.000s 74.949us 5 5 100.00
sec_cm_addr_scramble 5 5 100.00
sram_ctrl_smoke 2.000s 74.949us 5 5 100.00
sec_cm_instr_bus_lc_gated 5 5 100.00
sram_ctrl_executable 17.000s 2262.990us 5 5 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 2691.387us 5 5 100.00
sec_cm_key_global_esc 5 5 100.00
sram_ctrl_lc_escalation 11.000s 2804.231us 5 5 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 2691.387us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 2691.387us 5 5 100.00
sec_cm_scramble_key_sideload 5 5 100.00
sram_ctrl_smoke 2.000s 74.949us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 2691.387us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 5 100.00
sram_ctrl_stress_all_with_rand_reset 59.000s 2766.634us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 79458791083510093022082196481052851041136239984247057987817751766434237486142 88
UVM_INFO @ 29405170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---