Simulation Results: sysrst_ctrl

 
23/05/2026 11:52:00 DVSim: v1.49.0 sha: 21f062e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.22 %
  • code
  • 98.49 %
  • assert
  • 98.85 %
  • func
  • 88.32 %
  • line
  • 99.44 %
  • branch
  • 99.52 %
  • cond
  • 97.98 %
  • toggle
  • 100.00 %
  • FSM
  • 95.51 %
Validation stages
V1
100.00%
V2
98.61%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
sysrst_ctrl_smoke 9.020s 2112.781us 50 50 100.00
input_output_inverted 50 50 100.00
sysrst_ctrl_in_out_inverted 10.810s 2461.546us 50 50 100.00
combo_detect_ec_rst 5 5 100.00
sysrst_ctrl_combo_detect_ec_rst 7.950s 2389.668us 5 5 100.00
combo_detect_ec_rst_with_pre_cond 5 5 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 9.740s 2514.692us 5 5 100.00
csr_hw_reset 5 5 100.00
sysrst_ctrl_csr_hw_reset 23.850s 6048.932us 5 5 100.00
csr_rw 20 20 100.00
sysrst_ctrl_csr_rw 8.320s 2032.441us 20 20 100.00
csr_bit_bash 5 5 100.00
sysrst_ctrl_csr_bit_bash 162.270s 74377.064us 5 5 100.00
csr_aliasing 5 5 100.00
sysrst_ctrl_csr_aliasing 12.130s 2692.538us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 9.680s 2080.471us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sysrst_ctrl_csr_rw 8.320s 2032.441us 20 20 100.00
sysrst_ctrl_csr_aliasing 12.130s 2692.538us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 50 50 100.00
sysrst_ctrl_combo_detect 457.930s 216633.116us 50 50 100.00
combo_detect_with_pre_cond 94 100 94.00
sysrst_ctrl_combo_detect_with_pre_cond 391.460s 152740.266us 94 100 94.00
auto_block_key_outputs 50 50 100.00
sysrst_ctrl_auto_blk_key_output 681.360s 243936.476us 50 50 100.00
keyboard_input_triggered_interrupt 50 50 100.00
sysrst_ctrl_edge_detect 272.420s 164492.410us 50 50 100.00
pin_output_keyboard_inversion_control 50 50 100.00
sysrst_ctrl_pin_override_test 10.900s 2509.558us 50 50 100.00
pin_input_value_accessibility 50 50 100.00
sysrst_ctrl_pin_access_test 9.380s 2151.363us 50 50 100.00
ec_power_on_reset 48 50 96.00
sysrst_ctrl_ec_pwr_on_rst 469.990s 191559.605us 48 50 96.00
flash_write_protect_output 50 50 100.00
sysrst_ctrl_flash_wr_prot_out 10.450s 2614.018us 50 50 100.00
ultra_low_power_test 48 50 96.00
sysrst_ctrl_ultra_low_pwr 382.180s 1635771.530us 48 50 96.00
sysrst_ctrl_feature_disable 2 2 100.00
sysrst_ctrl_feature_disable 55.180s 35246.496us 2 2 100.00
stress_all 50 50 100.00
sysrst_ctrl_stress_all 906.300s 326555.018us 50 50 100.00
alert_test 50 50 100.00
sysrst_ctrl_alert_test 8.910s 2011.521us 50 50 100.00
intr_test 50 50 100.00
sysrst_ctrl_intr_test 8.500s 2009.984us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sysrst_ctrl_tl_errors 10.110s 2121.536us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sysrst_ctrl_tl_errors 10.110s 2121.536us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sysrst_ctrl_csr_hw_reset 23.850s 6048.932us 5 5 100.00
sysrst_ctrl_csr_rw 8.320s 2032.441us 20 20 100.00
sysrst_ctrl_csr_aliasing 12.130s 2692.538us 5 5 100.00
sysrst_ctrl_same_csr_outstanding 31.130s 9191.169us 20 20 100.00
tl_d_partial_access 50 50 100.00
sysrst_ctrl_csr_hw_reset 23.850s 6048.932us 5 5 100.00
sysrst_ctrl_csr_rw 8.320s 2032.441us 20 20 100.00
sysrst_ctrl_csr_aliasing 12.130s 2692.538us 5 5 100.00
sysrst_ctrl_same_csr_outstanding 31.130s 9191.169us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
sysrst_ctrl_sec_cm 100.400s 42018.657us 5 5 100.00
sysrst_ctrl_tl_intg_err 106.210s 42509.545us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
sysrst_ctrl_tl_intg_err 106.210s 42509.545us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 50 50 100.00
sysrst_ctrl_stress_all_with_rand_reset 25.520s 13171.945us 50 50 100.00

Error Messages

   Test seed line log context
UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == * 2 test runs
sysrst_ctrl_ec_pwr_on_rst 11461572163341057326056862821000047383740726995424442946563773830805344486617 657
UVM_INFO @ 2698108444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_ec_pwr_on_rst 39948312332924572143985412415791303832931598728347097706369288546352095388911 657
UVM_INFO @ 2291433208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)  2 test runs
sysrst_ctrl_ultra_low_pwr 15707320583487840048344204859295573297236866621422245862490779237801924841500 657
UVM_INFO @ 7913359583 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
UVM_INFO @ 10798359583 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 10833445578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sysrst_ctrl_ultra_low_pwr 72615627674927934650711012731626633910494828671845793555328239879040453991094 657
UVM_ERROR @ 1635771529628 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 1635771529628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(6) vs exp(2) +/-* 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 64362623753090037660185698314606478560007964484886994643765305556646090671855 694
UVM_ERROR @ 37456312360 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(6) vs exp(2) +/-4
UVM_INFO @ 37456312360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*]) 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 95717424983824500932771915038365354129398006415992133911043486632470290465546 680
UVM_ERROR @ 19477067175 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 1 [0x1])
UVM_INFO @ 19477067175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 12416148018096022175204083339705542275030968796240111320592581196670918592936 687
UVM_INFO @ 36084620822 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 36104620822 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 46231704544 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x19
UVM_INFO @ 46231844544 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0xe
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(7) vs exp(2) +/-* 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 70367802607964864873602253645641460406681898060451406239869089614805224391804 665
UVM_ERROR @ 17748433404 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(2) +/-4
UVM_INFO @ 17748433404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(10) vs exp(5) +/-* 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 61048243851341414617103705609854082426594420816517891379636974400759108713122 665
UVM_ERROR @ 16022501885 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(10) vs exp(5) +/-4
UVM_INFO @ 16022501885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(3) +/-* 1 test run
sysrst_ctrl_combo_detect_with_pre_cond 77878698272846504030463900570413685849933099828520850315298488374836386145237 668
UVM_ERROR @ 13191860341 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(7) vs exp(3) +/-4
UVM_INFO @ 13191860341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---