Simulation Results

Simulation Results: adc_ctrl

30/05/2026 15:09:44 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
67.48 %

code
96.23 %

assert
92.54 %

func
13.66 %

line
98.96 %

branch
97.59 %

cond
87.55 %

toggle
99.76 %

FSM
97.30 %

Validation stages

V1		100.00%
V2		50.85%
V2S		100.00%
V3		10.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	adc_ctrl_smoke	16.550s	5897.131us	10	10	100.00
csr_hw_reset				1	1	100.00
	adc_ctrl_csr_hw_reset	2.170s	708.677us	1	1	100.00
csr_rw				5	5	100.00
	adc_ctrl_csr_rw	1.930s	581.098us	5	5	100.00
csr_bit_bash				1	1	100.00
	adc_ctrl_csr_bit_bash	16.810s	26995.249us	1	1	100.00
csr_aliasing				1	1	100.00
	adc_ctrl_csr_aliasing	3.470s	905.186us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	adc_ctrl_csr_mem_rw_with_rand_reset	2.440s	506.567us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	adc_ctrl_csr_rw	1.930s	581.098us	5	5	100.00
	adc_ctrl_csr_aliasing	3.470s	905.186us	1	1	100.00

90/177 passed

50.85 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
filters_polled				0	10	0.00
	adc_ctrl_filters_polled	2.280s	451.334us	0	10	0.00
filters_polled_fixed				0	10	0.00
	adc_ctrl_filters_polled_fixed	2.390s	475.943us	0	10	0.00
filters_interrupt				0	10	0.00
	adc_ctrl_filters_interrupt	2.110s	490.400us	0	10	0.00
filters_interrupt_fixed				0	10	0.00
	adc_ctrl_filters_interrupt_fixed	2.440s	506.890us	0	10	0.00
filters_wakeup				0	10	0.00
	adc_ctrl_filters_wakeup	2.470s	470.874us	0	10	0.00
filters_wakeup_fixed				0	10	0.00
	adc_ctrl_filters_wakeup_fixed	2.280s	434.994us	0	10	0.00
filters_both				0	10	0.00
	adc_ctrl_filters_both	2.010s	329.450us	0	10	0.00
clock_gating				0	10	0.00
	adc_ctrl_clock_gating	2.260s	426.494us	0	10	0.00
poweron_counter				10	10	100.00
	adc_ctrl_poweron_counter	16.240s	5352.788us	10	10	100.00
lowpower_counter				10	10	100.00
	adc_ctrl_lowpower_counter	89.850s	44839.972us	10	10	100.00
fsm_reset				10	10	100.00
	adc_ctrl_fsm_reset	191.300s	96210.970us	10	10	100.00
stress_all				3	10	30.00
	adc_ctrl_stress_all	88.760s	52819.507us	3	10	30.00
alert_test				10	10	100.00
	adc_ctrl_alert_test	2.250s	420.233us	10	10	100.00
intr_test				10	10	100.00
	adc_ctrl_intr_test	2.360s	515.231us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	adc_ctrl_tl_errors	4.320s	563.862us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	adc_ctrl_tl_errors	4.320s	563.862us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	adc_ctrl_csr_hw_reset	2.170s	708.677us	1	1	100.00
	adc_ctrl_csr_rw	1.930s	581.098us	5	5	100.00
	adc_ctrl_csr_aliasing	3.470s	905.186us	1	1	100.00
	adc_ctrl_same_csr_outstanding	14.770s	4999.976us	5	5	100.00
tl_d_partial_access				12	12	100.00
	adc_ctrl_csr_hw_reset	2.170s	708.677us	1	1	100.00
	adc_ctrl_csr_rw	1.930s	581.098us	5	5	100.00
	adc_ctrl_csr_aliasing	3.470s	905.186us	1	1	100.00
	adc_ctrl_same_csr_outstanding	14.770s	4999.976us	5	5	100.00

V2S

30/30 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	adc_ctrl_sec_cm	23.770s	8198.107us	5	5	100.00
	adc_ctrl_tl_intg_err	27.820s	8206.535us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	adc_ctrl_tl_intg_err	27.820s	8206.535us	25	25	100.00

1/10 passed

10.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	10	10.00
	adc_ctrl_stress_all_with_rand_reset	13.470s	2983.888us	1	10	10.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [, ]				96 test runs
	adc_ctrl_filters_polled	86916044892290088473057457700863775869746908875082667959808987437578294533298	388	UVM_INFO @ 525920118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	68283527343397927539941919533896965453026453183553432631438906534780379957262	388	UVM_INFO @ 418913238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	20282095820186965184183536834260249732872227235979862308251654438805301232363	388	UVM_INFO @ 486414646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	107712653728406295579529214114643911014184291693176699675275782730334549099861	388	UVM_INFO @ 442066963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	34600966597912868867845347914697858686157617964208478339995517218283769913577	388	UVM_INFO @ 315455587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	50272354459065877332404474974898609976849193493075611172904834960333047087839	388	UVM_INFO @ 434993758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	3902644880164165132830446120100123144902264232427326576151269496944107434845	388	UVM_INFO @ 412396565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	10614789040177274254482900117456056449558292444832810688742682087048932464253	388	UVM_INFO @ 329450364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	70436419722532116366649121665245723657428977610560960126269556269781225720533	469	UVM_INFO @ 3695020545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	27064337099438866126157240433017666549801653372800227040011405926082497371263	388	UVM_INFO @ 522469860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	83931170339123301607354403414272343264411333104566317148458813091828909137017	388	UVM_INFO @ 328912522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	63940057339336178742865700207349285894968748272635004618855228942665031045568	388	UVM_INFO @ 311150118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	22859763215511740003754352536115308392741795774364354644181058489937727734472	388	UVM_INFO @ 378042645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	56158621547971696504099012996620036583697537941513264503427064350165849277843	388	UVM_INFO @ 284807355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	104386317843701291181203812933706294616335709790345914666547468653230866861456	388	UVM_INFO @ 348942313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	92456752870160479485336080226585935813909052403154622365849333953594561783825	388	UVM_INFO @ 374645499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	25147434547726803022176200715524794356336511839367188444786290286300700080167	388	UVM_INFO @ 384421564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	86354890040755278914394480487035467457174947071209180630690383736669404802572	401	UVM_INFO @ 852717448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	33912842980967924445131018429688657318051657673746052614580797283448062126970	528	UVM_INFO @ 52819506611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	91705329657894936446612081822035501348913803379030558563146960947254875669174	388	UVM_INFO @ 515197646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	96321462826159612467872052350806841856802524072872438062335675906512489520882	388	UVM_INFO @ 392090986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	45349013883257169257847611297736158861880532119819034953367653989323450205531	388	UVM_INFO @ 393571355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	64136903073874273941487936992692850090662854579100488474177273386698252509271	388	UVM_INFO @ 373750376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	27344456902373287946733387881766759924732513373164950709668408387593017786285	388	UVM_INFO @ 356426196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	97722466141436659092999259082245171978564522113010466180988737614237294389502	388	UVM_INFO @ 482650367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	113228591569133118693176981686814863161089189551886773816214384558419218159521	388	UVM_INFO @ 426493577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	108630687177245851410171785040583477260080149924585844889358512902059864511678	388	UVM_INFO @ 524434951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	97168025367980373653673665842502699943877564056370209199616463382239380449408	434	UVM_INFO @ 2842770260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	22941102806123865751913877819843852876198126717302473537269146968884489524064	389	UVM_INFO @ 883582217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	111988881090368206482630745000905572966682464870642176313641448250057047004626	388	UVM_INFO @ 408064669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	43663138565664101387929391866198730510347343788395741176877601127901133865893	388	UVM_INFO @ 461096808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	19216717646354805785681207367324575509213136727317860723609333243433951275096	388	UVM_INFO @ 485184747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	36729356594655761394713824150096075913190403822326446426502125733767180552271	388	UVM_INFO @ 506890393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	62771677529050563212639673141503186606088068092026054455245827463011600566419	388	UVM_INFO @ 421070787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	14781957772015339233364394680706751946786194228375716453566650133035519526451	388	UVM_INFO @ 493072427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	53651554670349653947109700289562261095083605223229263965394807396951037429262	388	UVM_INFO @ 276696496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	39985044565089404098437630278004758962390132819734072833393654034968461276005	388	UVM_INFO @ 456712093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	17848623471959423385108573323603838967089407480814042251649373033880699679847	467	UVM_INFO @ 4355871599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	95051166382662606948950582120140737598919004058573413044145752481433665759583	389	UVM_INFO @ 827709791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	15850008544291008037400097488077477302372367865513295781728702149000871073217	388	UVM_INFO @ 313341321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	115365998097308745523283048683426795045257686855041668863237125676788074034739	388	UVM_INFO @ 475943397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	11975643196477692715823603108606088802153148814536993656466608138951319982506	388	UVM_INFO @ 448750001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	87900960723726205336505602898624603247379890314273985758998328559931907088096	388	UVM_INFO @ 378587426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	38548041950796059166341069906415119272579146592890591957600092624124209712992	388	UVM_INFO @ 374689044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	14913912505739691593193536168503368737011197857201214820165901171838023092689	388	UVM_INFO @ 500582055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	53437563313280568243540317630410547433755345298769376829265004530650940703376	388	UVM_INFO @ 447811340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	75934124500194948721086118024736695103245923593139712534867242873614933292373	388	UVM_INFO @ 281368714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	75044783174451894908983975990474303135296861304506413654907449887252978869568	394	UVM_INFO @ 894133044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	60718656844734229084946721257145123568242286052831033227593900742489391187150	388	UVM_INFO @ 364800958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	103983759678401059135148746385261107148367971868573177813522360992417610900889	388	UVM_INFO @ 513592750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	83679081893450503771891215979460409679809786380077541482636014120254133037701	388	UVM_INFO @ 490400271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	115071966016253191526818034425029894006991465214691392589236267590760494965067	388	UVM_INFO @ 416506855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	26047379853112782673553667483011858948332415205805376431207627004808900237631	388	UVM_INFO @ 323161695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	65714105233409144726239032285738192551463429311636223174837045985482182374715	388	UVM_INFO @ 449618423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	93883816996576158179376241406947272158131495283589404250947735693464398662706	388	UVM_INFO @ 469405348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	22253649677886793428828765769178782043610893473843263090163042290251032393995	388	UVM_INFO @ 528775711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	104885460980443727204409944354548630891687026347159454991679787422683340197941	408	UVM_INFO @ 895270128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	2288107164320764003696939176641580547034288865408435819346447582977204636968	388	UVM_INFO @ 487087679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	53861659528145603748314201707044193325741128867459207976502577875089544127341	388	UVM_INFO @ 330767948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	69635123870331247997196534330454423130907526977503038582249064732474966220284	388	UVM_INFO @ 438350641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	16840389536858976990025839493029825390454103494243095447295949240985836081774	388	UVM_INFO @ 499584501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	53710427629601302711988936720973041393856664493466926035461050454196610546027	388	UVM_INFO @ 470873854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	56869827589851539898401168009947753790988743151158970570596154516733894265243	388	UVM_INFO @ 514687679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	7607087326118705676122005953094604481679574421380984609476385797718440577745	388	UVM_INFO @ 464100379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	68583415262594965451499407226775119778221547602811083293719514174531573484699	388	UVM_INFO @ 421696186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	105018912409764747497375890567176247619731002908452614005550782391894343729981	401	UVM_INFO @ 742670323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	79807954359402534227692962413364192848686056253889002819882928117121800590301	389	UVM_INFO @ 872212709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	54875366084350776899358983378261401503333131976244148308172726854682515532508	388	UVM_INFO @ 488870763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	53936425422261022767682736072091760181791660502833787896024029477674942011194	388	UVM_INFO @ 418470336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	57480630730648732868392876805943745533737020795376675479091815727516014877048	388	UVM_INFO @ 443805607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	16561370384857582773940276151028146230148426660513286683345273240119895030033	388	UVM_INFO @ 296537982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	100681653359561788227982355654121173642403420511314039590848988283194069792868	388	UVM_INFO @ 523286944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	94299618532386473370425989785016362506307203890781130544171081063317207161509	388	UVM_INFO @ 481824480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	108364529494806770689522065498417283168949331861228628304450602545606342566781	388	UVM_INFO @ 313808091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	106608772784311488683622769392046428232507415225249338996465711574528478662171	388	UVM_INFO @ 448832908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	48139078776877980312958117229375995838535899136698201704527794660384484402578	415	UVM_INFO @ 1011131004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	10377988055015377898482541813732357207328116369417969513050029058995605530174	389	UVM_INFO @ 979788022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	27366593195487366461046613728239223546107265999090491291241767123407843437973	388	UVM_INFO @ 451334412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	82240849318837193328662204092382596708069332480553326831052683983283720886104	388	UVM_INFO @ 290586177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	63989219054677753531176733227748082185477409740259597042426201452666860187792	388	UVM_INFO @ 295845201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	70232387145096395984733648555584642789154596719477738490539283268846316445312	388	UVM_INFO @ 518911986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	29124341321934713184461786759898274721953244398631350491194585785500345847247	388	UVM_INFO @ 289879715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	67051090281701432186294788357152372945048274744764762421625923916100342255104	388	UVM_INFO @ 515669532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	71087789064336470161258321778719732442067743371416113920137089453029418768684	388	UVM_INFO @ 399036718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	72635800638218306652028838592284889421215027281606493545252594365770390804292	388	UVM_INFO @ 408681185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	98889060015702224757717583961279349778421795481799440838285043045361171062961	407	UVM_INFO @ 1306625063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	56145678910317193151291889042322294293960548201224791025926061210818811753945	496	UVM_INFO @ 45535097217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	57991759471428258765074558333510848874706723152005030839133103485268881854049	388	UVM_INFO @ 342904512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	113470918702295169715657343076680311043910518941551331350431468085398430008751	388	UVM_INFO @ 500821850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	101302680785017557904112894790664744992394268140816629787854106192182918743945	388	UVM_INFO @ 362382722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	4473192298516334918192375331673829911066316124273678734649952737706629468321	388	UVM_INFO @ 302188395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	77391573693484222382513381983011117303993308582983680586870082586865726280406	388	UVM_INFO @ 279690051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	110974938360563624112757175816171322859458685192490922232194898151707551291400	388	UVM_INFO @ 457520496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	69618800715476957789279920983377411658559256931013727711655602789007616097268	388	UVM_INFO @ 474259168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	57397691047876541637324415417996656077807476762619508115231532988198821310247	388	UVM_INFO @ 411394103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	84588798059197632090653083078911371020819275760740716569991242440860619776910	389	UVM_INFO @ 850985749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---