Simulation Results: aes/masked

 
30/05/2026 15:09:44 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.90 %
  • code
  • 96.67 %
  • assert
  • 98.38 %
  • func
  • 98.65 %
  • block
  • 97.03 %
  • line
  • 98.15 %
  • branch
  • 92.67 %
  • toggle
  • 98.08 %
  • FSM
  • 97.78 %
Validation stages
V1
100.00%
V2
99.54%
V2S
92.24%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 64.007us 1 1 100.00
smoke 10 10 100.00
aes_smoke 4.000s 91.778us 10 10 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 89.229us 1 1 100.00
csr_rw 5 5 100.00
aes_csr_rw 2.000s 67.310us 5 5 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 7.000s 1546.342us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 15.000s 661.943us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
aes_csr_mem_rw_with_rand_reset 3.000s 104.667us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
aes_csr_rw 2.000s 67.310us 5 5 100.00
aes_csr_aliasing 15.000s 661.943us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 70 70 100.00
aes_smoke 4.000s 91.778us 10 10 100.00
aes_config_error 28.000s 192.335us 50 50 100.00
aes_stress 7.000s 400.550us 10 10 100.00
key_length 70 70 100.00
aes_smoke 4.000s 91.778us 10 10 100.00
aes_config_error 28.000s 192.335us 50 50 100.00
aes_stress 7.000s 400.550us 10 10 100.00
back2back 35 35 100.00
aes_stress 7.000s 400.550us 10 10 100.00
aes_b2b 32.000s 81.869us 25 25 100.00
backpressure 10 10 100.00
aes_stress 7.000s 400.550us 10 10 100.00
multi_message 94 95 98.95
aes_smoke 4.000s 91.778us 10 10 100.00
aes_config_error 28.000s 192.335us 50 50 100.00
aes_stress 7.000s 400.550us 10 10 100.00
aes_alert_reset 35.000s 535.626us 24 25 96.00
failure_test 84 85 98.82
aes_man_cfg_err 3.000s 71.446us 10 10 100.00
aes_config_error 28.000s 192.335us 50 50 100.00
aes_alert_reset 35.000s 535.626us 24 25 96.00
trigger_clear_test 10 10 100.00
aes_clear 28.000s 98.542us 10 10 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 11.000s 171.599us 1 1 100.00
reset_recovery 24 25 96.00
aes_alert_reset 35.000s 535.626us 24 25 96.00
stress 10 10 100.00
aes_stress 7.000s 400.550us 10 10 100.00
sideload 20 20 100.00
aes_stress 7.000s 400.550us 10 10 100.00
aes_sideload 8.000s 116.688us 10 10 100.00
deinitialization 10 10 100.00
aes_deinit 6.000s 450.632us 10 10 100.00
stress_all 10 10 100.00
aes_stress_all 44.000s 1119.082us 10 10 100.00
alert_test 10 10 100.00
aes_alert_test 30.000s 55.946us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
aes_tl_errors 4.000s 99.659us 25 25 100.00
tl_d_illegal_access 25 25 100.00
aes_tl_errors 4.000s 99.659us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
aes_csr_hw_reset 2.000s 89.229us 1 1 100.00
aes_csr_rw 2.000s 67.310us 5 5 100.00
aes_csr_aliasing 15.000s 661.943us 1 1 100.00
aes_same_csr_outstanding 3.000s 85.447us 5 5 100.00
tl_d_partial_access 12 12 100.00
aes_csr_hw_reset 2.000s 89.229us 1 1 100.00
aes_csr_rw 2.000s 67.310us 5 5 100.00
aes_csr_aliasing 15.000s 661.943us 1 1 100.00
aes_same_csr_outstanding 3.000s 85.447us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 10 10 100.00
aes_reseed 18.000s 1002.845us 10 10 100.00
fault_inject 591 660 89.55
aes_fi 5.000s 101.924us 10 10 100.00
aes_control_fi 61.000s 0.000us 260 300 86.67
aes_cipher_fi 61.000s 0.000us 321 350 91.71
shadow_reg_update_error 20 20 100.00
aes_shadow_reg_errors 3.000s 171.215us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
aes_shadow_reg_errors 3.000s 171.215us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
aes_shadow_reg_errors 3.000s 171.215us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
aes_shadow_reg_errors 3.000s 171.215us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 556.273us 20 20 100.00
tl_intg_err 30 30 100.00
aes_sec_cm 5.000s 463.097us 5 5 100.00
aes_tl_intg_err 4.000s 174.238us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
aes_tl_intg_err 4.000s 174.238us 25 25 100.00
sec_cm_lc_escalate_en_intersig_mubi 24 25 96.00
aes_alert_reset 35.000s 535.626us 24 25 96.00
sec_cm_main_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 171.215us 20 20 100.00
sec_cm_gcm_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 171.215us 20 20 100.00
sec_cm_main_config_sparse 138 145 95.17
aes_smoke 4.000s 91.778us 10 10 100.00
aes_stress 7.000s 400.550us 10 10 100.00
aes_alert_reset 35.000s 535.626us 24 25 96.00
aes_core_fi 65.000s 10015.483us 94 100 94.00
sec_cm_gcm_config_sparse 154 160 96.25
aes_config_error 28.000s 192.335us 50 50 100.00
aes_stress 7.000s 400.550us 10 10 100.00
aes_core_fi 65.000s 10015.483us 94 100 94.00
sec_cm_aux_config_shadow 20 20 100.00
aes_shadow_reg_errors 3.000s 171.215us 20 20 100.00
sec_cm_aux_config_regwen 20 20 100.00
aes_readability 3.000s 92.252us 10 10 100.00
aes_stress 7.000s 400.550us 10 10 100.00
sec_cm_key_sideload 20 20 100.00
aes_stress 7.000s 400.550us 10 10 100.00
aes_sideload 8.000s 116.688us 10 10 100.00
sec_cm_key_sw_unreadable 10 10 100.00
aes_readability 3.000s 92.252us 10 10 100.00
sec_cm_data_reg_sw_unreadable 10 10 100.00
aes_readability 3.000s 92.252us 10 10 100.00
sec_cm_key_sec_wipe 10 10 100.00
aes_readability 3.000s 92.252us 10 10 100.00
sec_cm_iv_config_sec_wipe 10 10 100.00
aes_readability 3.000s 92.252us 10 10 100.00
sec_cm_data_reg_sec_wipe 10 10 100.00
aes_readability 3.000s 92.252us 10 10 100.00
sec_cm_data_reg_key_sca 10 10 100.00
aes_stress 7.000s 400.550us 10 10 100.00
sec_cm_key_masking 10 10 100.00
aes_stress 7.000s 400.550us 10 10 100.00
sec_cm_main_fsm_sparse 10 10 100.00
aes_fi 5.000s 101.924us 10 10 100.00
sec_cm_main_fsm_redun 616 685 89.93
aes_fi 5.000s 101.924us 10 10 100.00
aes_control_fi 61.000s 0.000us 260 300 86.67
aes_cipher_fi 61.000s 0.000us 321 350 91.71
aes_ctr_fi 30.000s 48.942us 25 25 100.00
sec_cm_cipher_fsm_sparse 10 10 100.00
aes_fi 5.000s 101.924us 10 10 100.00
sec_cm_cipher_fsm_redun 591 660 89.55
aes_fi 5.000s 101.924us 10 10 100.00
aes_control_fi 61.000s 0.000us 260 300 86.67
aes_cipher_fi 61.000s 0.000us 321 350 91.71
sec_cm_cipher_ctr_redun 321 350 91.71
aes_cipher_fi 61.000s 0.000us 321 350 91.71
sec_cm_ctr_fsm_sparse 10 10 100.00
aes_fi 5.000s 101.924us 10 10 100.00
sec_cm_ctr_fsm_redun 295 335 88.06
aes_fi 5.000s 101.924us 10 10 100.00
aes_control_fi 61.000s 0.000us 260 300 86.67
aes_ctr_fi 30.000s 48.942us 25 25 100.00
sec_cm_ghash_fsm_sparse 10 10 100.00
aes_fi 5.000s 101.924us 10 10 100.00
sec_cm_ctrl_sparse 616 685 89.93
aes_fi 5.000s 101.924us 10 10 100.00
aes_control_fi 61.000s 0.000us 260 300 86.67
aes_cipher_fi 61.000s 0.000us 321 350 91.71
aes_ctr_fi 30.000s 48.942us 25 25 100.00
sec_cm_main_fsm_global_esc 24 25 96.00
aes_alert_reset 35.000s 535.626us 24 25 96.00
sec_cm_main_fsm_local_esc 616 685 89.93
aes_fi 5.000s 101.924us 10 10 100.00
aes_control_fi 61.000s 0.000us 260 300 86.67
aes_cipher_fi 61.000s 0.000us 321 350 91.71
aes_ctr_fi 30.000s 48.942us 25 25 100.00
sec_cm_cipher_fsm_local_esc 616 685 89.93
aes_fi 5.000s 101.924us 10 10 100.00
aes_control_fi 61.000s 0.000us 260 300 86.67
aes_cipher_fi 61.000s 0.000us 321 350 91.71
aes_ctr_fi 30.000s 48.942us 25 25 100.00
sec_cm_ctr_fsm_local_esc 295 335 88.06
aes_fi 5.000s 101.924us 10 10 100.00
aes_control_fi 61.000s 0.000us 260 300 86.67
aes_ctr_fi 30.000s 48.942us 25 25 100.00
sec_cm_ghash_fsm_local_esc 10 10 100.00
aes_fi 5.000s 101.924us 10 10 100.00
sec_cm_data_reg_local_esc 591 660 89.55
aes_fi 5.000s 101.924us 10 10 100.00
aes_control_fi 61.000s 0.000us 260 300 86.67
aes_cipher_fi 61.000s 0.000us 321 350 91.71
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
aes_stress_all_with_rand_reset 62.000s 4075.859us 0 10 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 24 test runs
aes_cipher_fi 40585994366294959918882195131151434192153497507530448688903844194473602984498 147
UVM_INFO @ 10006668067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 104038580883466116215407337898549709479920139618644312007471779466704547686018 140
UVM_INFO @ 10010032804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 43181437858693903281514214305055671703966393626250395143032425423933503093331 145
UVM_INFO @ 10012836700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 113463043641574023895564203496580885259887728239162075288157008134479640481304 146
UVM_INFO @ 10009737887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 18953497427692656251140331388478988307964461697718851074331604955251373787081 140
UVM_INFO @ 10185334955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 83559071247780513335811567057969428989029420292283155421096229318035839061264 145
UVM_INFO @ 10002830325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 14753676932230608204573042845261272674379125762010897118560831496869879399860 147
UVM_INFO @ 10039305440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 64382751548586800093125499925914221434126722033590354368384344184984180894624 150
UVM_INFO @ 10031584845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 21151285926483367931911077839446938116564176022083339768178526293278074320271 146
UVM_INFO @ 10027529186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 29634839769267657894207617219245327208508786078916265968362788640740838438250 149
UVM_INFO @ 10011155951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 24413639061723954308684777895370061347403335695038669447096890450877936899713 141
UVM_INFO @ 10200084383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 42877571620560112200473110009302755334672146327052744878687808451779956385005 143
UVM_INFO @ 10198306104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 53226172638950449001285020122630376121626347923593693070801569586615213659280 148
UVM_INFO @ 10013917868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 109958117082518026202479417098726692310985511560170376413875133616631959528599 149
UVM_INFO @ 10025436505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 4882875999412786148210167894821730868291039699631726388456826680134101404404 151
UVM_INFO @ 10014875374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 97377969134141950148026079665421291728884385294139014801818895476961799953254 139
UVM_INFO @ 10012847474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 54740881994769268557406486822084139608554211309115742689615249177288094785016 145
UVM_INFO @ 10068247770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 35309041255520242043953124799047039370414184808711107879414168422403705793337 145
UVM_INFO @ 10011118958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 88894919366018483875884641673437405938740094228056591532608981329566224545520 137
UVM_INFO @ 10015860854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 11264554843860551619682209236504772953211412623250881593304999925434244679418 140
UVM_INFO @ 10057649169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 94246701423363838079050400029407384688984544037752750715156559853620162862613 145
UVM_INFO @ 10047793372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 31464415923343096250236648536676549411892371701497169393063566990857975582210 142
UVM_INFO @ 10005522015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 18971393963696221932965694439045381886873354462527346289949326490175029578598 142
UVM_INFO @ 10014509045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 115488041075234231894536979460753425788028956605979273530563361974676772506918 150
UVM_INFO @ 10036654096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 24 test runs
aes_control_fi 61639342090125798371248709499225813625941788759085243651075449484016059780151 151
UVM_INFO @ 10009654767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 73303537052733915246372248149138392617645738872643082994346166693065195895137 148
UVM_INFO @ 10068128912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 65049826580570557214750862764092217056780261259719569773943524819060209532876 150
UVM_INFO @ 10020831414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 67086807162310074161511743270477438178321855387991209045237658499433845024939 151
UVM_INFO @ 10013668408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 17349214580412706156356345849899560378707788693699772382438544731362153754338 144
UVM_INFO @ 10018743151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 101039799295958128239673499730226828966661969062363653874157903539616316615989 142
UVM_INFO @ 10005802375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 30071522860557228794913274289174915716617467949793368135221182210937382929227 148
UVM_INFO @ 10007623233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 44793447764174283676157518477260603517426770604202596843176903399044065812922 150
UVM_INFO @ 10014203315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 22984781294763970579194573688715185998591633024930101191234082185038620540914 141
UVM_INFO @ 10053005987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 47233143902403027342687064997515845594108947709554149992247553296102128229567 148
UVM_INFO @ 10011531061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 6138520358255759744785953462412980518321166670998171276130622704657827656573 138
UVM_INFO @ 10060788102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 84114062053248815862721335191985760616571414901428320481973239020897784372030 145
UVM_INFO @ 10025424807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 73792017545736404859622188682840545049051269254759985074289173746994641452743 142
UVM_INFO @ 10008337860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 61708515560516474659266006408477156006367451897134082073792709876329072376255 143
UVM_INFO @ 10006562337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 32898924941286568566279390066524887855111139187190287001036347433988362987660 144
UVM_INFO @ 10007482001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 20492275092964483522134748851477031028783824142426647466771688707929335166381 144
UVM_INFO @ 10008903728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 76573365638489847271461583199966880622843749842078884096300330282112492021415 153
UVM_INFO @ 10008763373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 30202389663624022865894695161011462330787507549263528595047979805135507429060 151
UVM_INFO @ 10015407356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 23052956587491762199723402169827366216702524680620642525660551572187093762232 153
UVM_INFO @ 10057012166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 80154780805957086998993599618044776944906484762511840453644430911661392674393 146
UVM_INFO @ 10019263551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 89774953009458736509108711232540778553059393653919703619432232720054758060046 156
UVM_INFO @ 10027101828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 17573092926005113824105642077706596933316212497251720451862417215356927854771 149
UVM_INFO @ 10027686778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 67615367893892437162286802302176821256344527243331341614626170171750736096658 143
UVM_INFO @ 10045675408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 56604755931247464528280810724177462582772794065094764924052887392758788442979 145
UVM_INFO @ 10006601663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 21 test runs
aes_control_fi 23689220962877487002262272257690010687677628391936244732890410777306508188003 None
aes_control_fi 68477737832136283944293307642185802015692617903919973873892761892796224198725 None
aes_control_fi 92168055360201514927313735151359623259936014657283922080789277160701295232720 None
aes_control_fi 49865093040990114401562687543176810241005767542870930196923752292083776471549 None
aes_control_fi 39351397122110900256552325546992253487742022304365554994351820539178910866710 None
aes_control_fi 86512652897268165007818256979914949274500631986749373276149112214906697716167 None
aes_control_fi 42740047501516332166497058259975774906226779534874506647777265172008095155038 None
aes_control_fi 98101714033904284979271316844152548983616446168450005242281858269941656970849 None
aes_control_fi 114832192882209878838188576656894308898502595426154357600344773546964725844948 None
aes_cipher_fi 100730196108926817606793404066744029587407518389317735919958997413861361567168 None
aes_control_fi 29740295882881213963957840751635110593379880424356294427910039779881598079093 None
aes_cipher_fi 102945689729740944328871910959718125447825877678446456949477447285184079251428 None
aes_control_fi 97393359282912893864180848068404313574525532432097171196627664911792595173368 None
aes_cipher_fi 105428349203220015760168352425588874386569655448569366235880127997411719116194 None
aes_control_fi 25492912216269065545394281593838837725068181981534372838015171917902896756183 None
aes_control_fi 56094589973458135854377283752683589919965381421110113940691292579347796004073 None
aes_control_fi 54076504523809027637246559306302728451791357956227239267629603040446297634348 None
aes_cipher_fi 20134013253170334055234483344331398734381468593377005065989871156729162795308 None
aes_control_fi 51471216014914595459280022306904226088826974753162380247330209960819569778714 None
aes_cipher_fi 19100829131391458247026458076181801260571559969080345372353377867020170996926 None
aes_control_fi 20746192144451665963847023682059841079443309540658810365977753084590391999884 None
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 8 test runs
aes_stress_all_with_rand_reset 70313178626107076645551792930421812781714925790309727158201468786913471568495 149
UVM_INFO @ 190593475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 29164841424273680797343864639246579214543459205512717211754509995495302613636 160
UVM_INFO @ 10031580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 64103205372275698796681389946409002107096564155728115797850465222611339843429 147
UVM_INFO @ 8833016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 103871391562072390639633840651829298809867554815000813403115338228735877897881 166
UVM_INFO @ 57937147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 56026507099945127892046471283927214555626749959665584642611782306012773084464 721
UVM_INFO @ 1266425177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 78194908374859940587160458555014115476668191538574853716464740586068320979314 138
UVM_INFO @ 133106551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 2797602453958476440688703884985005878710023000621507871639434056116511885677 493
UVM_INFO @ 2665040849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 109864588079045159466910437679379653456145991005127905314967985259076244828973 1564
UVM_INFO @ 4075858921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 6 test runs
aes_core_fi 115443527266917351463228320248059511647130038978497123474214771733166902280706 140
UVM_INFO @ 10016107972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 91460245690342970048553054826708625062143975591586525424000183913865255786084 149
UVM_INFO @ 10015482629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 31229894538654135010503252657318010350941265197798879046405249637542070244080 152
UVM_INFO @ 10014870239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 112620772019223910017949034308428975718319639949824150935643722805923209170783 150
UVM_INFO @ 10029193332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 68102679985599186212960942037403985215366435297578565890997252839534177942077 140
UVM_INFO @ 10072427911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 28073317251130267340597399282478145000067168974060685626357144417728896532368 146
UVM_INFO @ 10008394436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1112): Assertion AesModeValid has failed 2 test runs
aes_stress_all_with_rand_reset 53874716168205826470380037873829023971997008497034284165989198324024122248487 434
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 583552167 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[2].gen_fsm_n.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 583552167 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[1].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 583552167 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[0].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
UVM_ERROR @ 583552167 ps: (aes_core.sv:1112) [ASSERT FAILED] AesModeValid
aes_alert_reset 32956934046132540757629401586980315620300366697274579529693019655601137941257 404
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 6880449 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[2].gen_fsm_n.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 6880449 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[1].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_masked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 6880449 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[0].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
UVM_ERROR @ 6880449 ps: (aes_core.sv:1112) [ASSERT FAILED] AesModeValid
UVM_FATAL (aes_base_vseq.sv:1031) virtual_sequencer [aes_reseed_vseq] 1 test run
aes_stress_all_with_rand_reset 10455064836509467444513289603791499846992339071826455203244664356376353593031 712
Was able to clear FATAL ALERT without reset
---| Idle: 0
---| Stall: 0