Simulation Results: aes/unmasked

 
30/05/2026 15:09:44 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.05 %
  • code
  • 93.12 %
  • assert
  • 97.92 %
  • func
  • 97.10 %
  • block
  • 94.20 %
  • line
  • 95.75 %
  • branch
  • 87.65 %
  • toggle
  • 97.99 %
  • FSM
  • 91.11 %
Validation stages
V1
100.00%
V2
99.54%
V2S
91.43%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 188.507us 1 1 100.00
smoke 10 10 100.00
aes_smoke 3.000s 76.121us 10 10 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 88.905us 1 1 100.00
csr_rw 5 5 100.00
aes_csr_rw 2.000s 97.024us 5 5 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 115.934us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 119.960us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 79.299us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
aes_csr_rw 2.000s 97.024us 5 5 100.00
aes_csr_aliasing 3.000s 119.960us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 70 70 100.00
aes_smoke 3.000s 76.121us 10 10 100.00
aes_config_error 7.000s 372.636us 50 50 100.00
aes_stress 4.000s 123.160us 10 10 100.00
key_length 70 70 100.00
aes_smoke 3.000s 76.121us 10 10 100.00
aes_config_error 7.000s 372.636us 50 50 100.00
aes_stress 4.000s 123.160us 10 10 100.00
back2back 35 35 100.00
aes_stress 4.000s 123.160us 10 10 100.00
aes_b2b 8.000s 152.969us 25 25 100.00
backpressure 10 10 100.00
aes_stress 4.000s 123.160us 10 10 100.00
multi_message 94 95 98.95
aes_smoke 3.000s 76.121us 10 10 100.00
aes_config_error 7.000s 372.636us 50 50 100.00
aes_stress 4.000s 123.160us 10 10 100.00
aes_alert_reset 4.000s 106.680us 24 25 96.00
failure_test 84 85 98.82
aes_man_cfg_err 3.000s 56.483us 10 10 100.00
aes_config_error 7.000s 372.636us 50 50 100.00
aes_alert_reset 4.000s 106.680us 24 25 96.00
trigger_clear_test 10 10 100.00
aes_clear 4.000s 293.761us 10 10 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 10.000s 4820.472us 1 1 100.00
reset_recovery 24 25 96.00
aes_alert_reset 4.000s 106.680us 24 25 96.00
stress 10 10 100.00
aes_stress 4.000s 123.160us 10 10 100.00
sideload 20 20 100.00
aes_stress 4.000s 123.160us 10 10 100.00
aes_sideload 3.000s 87.741us 10 10 100.00
deinitialization 10 10 100.00
aes_deinit 3.000s 123.192us 10 10 100.00
stress_all 10 10 100.00
aes_stress_all 22.000s 1730.717us 10 10 100.00
alert_test 10 10 100.00
aes_alert_test 3.000s 54.820us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
aes_tl_errors 4.000s 159.489us 25 25 100.00
tl_d_illegal_access 25 25 100.00
aes_tl_errors 4.000s 159.489us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
aes_csr_hw_reset 2.000s 88.905us 1 1 100.00
aes_csr_rw 2.000s 97.024us 5 5 100.00
aes_csr_aliasing 3.000s 119.960us 1 1 100.00
aes_same_csr_outstanding 3.000s 65.295us 5 5 100.00
tl_d_partial_access 12 12 100.00
aes_csr_hw_reset 2.000s 88.905us 1 1 100.00
aes_csr_rw 2.000s 97.024us 5 5 100.00
aes_csr_aliasing 3.000s 119.960us 1 1 100.00
aes_same_csr_outstanding 3.000s 65.295us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 10 10 100.00
aes_reseed 5.000s 237.175us 10 10 100.00
fault_inject 592 660 89.70
aes_fi 4.000s 255.037us 10 10 100.00
aes_control_fi 61.000s 0.000us 267 300 89.00
aes_cipher_fi 61.000s 0.000us 315 350 90.00
shadow_reg_update_error 18 20 90.00
aes_shadow_reg_errors 10.000s 10058.589us 18 20 90.00
shadow_reg_read_clear_staged_value 18 20 90.00
aes_shadow_reg_errors 10.000s 10058.589us 18 20 90.00
shadow_reg_storage_error 18 20 90.00
aes_shadow_reg_errors 10.000s 10058.589us 18 20 90.00
shadowed_reset_glitch 18 20 90.00
aes_shadow_reg_errors 10.000s 10058.589us 18 20 90.00
shadow_reg_update_error_with_csr_rw 18 20 90.00
aes_shadow_reg_errors_with_csr_rw 13.000s 10017.038us 18 20 90.00
tl_intg_err 30 30 100.00
aes_sec_cm 5.000s 467.939us 5 5 100.00
aes_tl_intg_err 4.000s 1816.838us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
aes_tl_intg_err 4.000s 1816.838us 25 25 100.00
sec_cm_lc_escalate_en_intersig_mubi 24 25 96.00
aes_alert_reset 4.000s 106.680us 24 25 96.00
sec_cm_main_config_shadow 18 20 90.00
aes_shadow_reg_errors 10.000s 10058.589us 18 20 90.00
sec_cm_gcm_config_shadow 18 20 90.00
aes_shadow_reg_errors 10.000s 10058.589us 18 20 90.00
sec_cm_main_config_sparse 133 145 91.72
aes_smoke 3.000s 76.121us 10 10 100.00
aes_stress 4.000s 123.160us 10 10 100.00
aes_alert_reset 4.000s 106.680us 24 25 96.00
aes_core_fi 34.000s 10003.707us 89 100 89.00
sec_cm_gcm_config_sparse 149 160 93.12
aes_config_error 7.000s 372.636us 50 50 100.00
aes_stress 4.000s 123.160us 10 10 100.00
aes_core_fi 34.000s 10003.707us 89 100 89.00
sec_cm_aux_config_shadow 18 20 90.00
aes_shadow_reg_errors 10.000s 10058.589us 18 20 90.00
sec_cm_aux_config_regwen 20 20 100.00
aes_readability 3.000s 67.774us 10 10 100.00
aes_stress 4.000s 123.160us 10 10 100.00
sec_cm_key_sideload 20 20 100.00
aes_stress 4.000s 123.160us 10 10 100.00
aes_sideload 3.000s 87.741us 10 10 100.00
sec_cm_key_sw_unreadable 10 10 100.00
aes_readability 3.000s 67.774us 10 10 100.00
sec_cm_data_reg_sw_unreadable 10 10 100.00
aes_readability 3.000s 67.774us 10 10 100.00
sec_cm_key_sec_wipe 10 10 100.00
aes_readability 3.000s 67.774us 10 10 100.00
sec_cm_iv_config_sec_wipe 10 10 100.00
aes_readability 3.000s 67.774us 10 10 100.00
sec_cm_data_reg_sec_wipe 10 10 100.00
aes_readability 3.000s 67.774us 10 10 100.00
sec_cm_data_reg_key_sca 10 10 100.00
aes_stress 4.000s 123.160us 10 10 100.00
sec_cm_key_masking 10 10 100.00
aes_stress 4.000s 123.160us 10 10 100.00
sec_cm_main_fsm_sparse 10 10 100.00
aes_fi 4.000s 255.037us 10 10 100.00
sec_cm_main_fsm_redun 617 685 90.07
aes_fi 4.000s 255.037us 10 10 100.00
aes_control_fi 61.000s 0.000us 267 300 89.00
aes_cipher_fi 61.000s 0.000us 315 350 90.00
aes_ctr_fi 2.000s 165.395us 25 25 100.00
sec_cm_cipher_fsm_sparse 10 10 100.00
aes_fi 4.000s 255.037us 10 10 100.00
sec_cm_cipher_fsm_redun 592 660 89.70
aes_fi 4.000s 255.037us 10 10 100.00
aes_control_fi 61.000s 0.000us 267 300 89.00
aes_cipher_fi 61.000s 0.000us 315 350 90.00
sec_cm_cipher_ctr_redun 315 350 90.00
aes_cipher_fi 61.000s 0.000us 315 350 90.00
sec_cm_ctr_fsm_sparse 10 10 100.00
aes_fi 4.000s 255.037us 10 10 100.00
sec_cm_ctr_fsm_redun 302 335 90.15
aes_fi 4.000s 255.037us 10 10 100.00
aes_control_fi 61.000s 0.000us 267 300 89.00
aes_ctr_fi 2.000s 165.395us 25 25 100.00
sec_cm_ghash_fsm_sparse 10 10 100.00
aes_fi 4.000s 255.037us 10 10 100.00
sec_cm_ctrl_sparse 617 685 90.07
aes_fi 4.000s 255.037us 10 10 100.00
aes_control_fi 61.000s 0.000us 267 300 89.00
aes_cipher_fi 61.000s 0.000us 315 350 90.00
aes_ctr_fi 2.000s 165.395us 25 25 100.00
sec_cm_main_fsm_global_esc 24 25 96.00
aes_alert_reset 4.000s 106.680us 24 25 96.00
sec_cm_main_fsm_local_esc 617 685 90.07
aes_fi 4.000s 255.037us 10 10 100.00
aes_control_fi 61.000s 0.000us 267 300 89.00
aes_cipher_fi 61.000s 0.000us 315 350 90.00
aes_ctr_fi 2.000s 165.395us 25 25 100.00
sec_cm_cipher_fsm_local_esc 617 685 90.07
aes_fi 4.000s 255.037us 10 10 100.00
aes_control_fi 61.000s 0.000us 267 300 89.00
aes_cipher_fi 61.000s 0.000us 315 350 90.00
aes_ctr_fi 2.000s 165.395us 25 25 100.00
sec_cm_ctr_fsm_local_esc 302 335 90.15
aes_fi 4.000s 255.037us 10 10 100.00
aes_control_fi 61.000s 0.000us 267 300 89.00
aes_ctr_fi 2.000s 165.395us 25 25 100.00
sec_cm_ghash_fsm_local_esc 10 10 100.00
aes_fi 4.000s 255.037us 10 10 100.00
sec_cm_data_reg_local_esc 592 660 89.70
aes_fi 4.000s 255.037us 10 10 100.00
aes_control_fi 61.000s 0.000us 267 300 89.00
aes_cipher_fi 61.000s 0.000us 315 350 90.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
aes_stress_all_with_rand_reset 25.000s 5402.693us 0 10 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 28 test runs
aes_cipher_fi 48103443984164636924174151436761271205984339948078809372907100423451086383104 141
UVM_INFO @ 10006974333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 67422300050090343444632667588419234231578660534802457143341174141139832111973 152
UVM_INFO @ 10005191627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 95897000925347445526933772862212279689507801180878552349498081117550572880885 145
UVM_INFO @ 10016986752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 72435895377711026180913266490475251476808599703742248539967980202552231183875 153
UVM_INFO @ 10008817200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 54770012088269592421935599578935594905785194297478217822673917445831458453288 152
UVM_INFO @ 10004645801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 37823977859537167030384732338499476859648459360729744891703647914565817987761 143
UVM_INFO @ 10008890905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 107384105381854869242862086525863877657738221501841858405551747954224366532527 145
UVM_INFO @ 10028170766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 49435608611185571912078471435655336913796296736567662464638435048488044766071 143
UVM_INFO @ 10005827662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 4674150557290437820482504691293093556590657818304155229731232809321130784442 142
UVM_INFO @ 10020095798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 87937360060068933414716299958880927447572201238345329649635098013276749930774 149
UVM_INFO @ 10012089007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 90384298778634677258205978852666452975419553608702594998980866548643472104694 145
UVM_INFO @ 10003577747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 26456555064111511602335476247316042709351577797200067633348290183327649738391 146
UVM_INFO @ 10007122208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 75134264880025424735096961640223540989331861862744092021619971614009239485912 143
UVM_INFO @ 10006512379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 79251464250133316205494434814332483241851505689048084777453688367536276821431 146
UVM_INFO @ 10009185965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 6504891686583074196835572508347155634189768460099176910276014364667772675787 151
UVM_INFO @ 10011888623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 84328662071274293654777868092462855891428033949404474352512057595551157803133 154
UVM_INFO @ 10003661775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 75130806548384128113275222436474421006114524873102271667790091247016542552131 147
UVM_INFO @ 10012046531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 75846937650369099206005608735162714760078917821632184732648874112575172438509 145
UVM_INFO @ 10005713721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 25220702537795137031355717480871284188362491899596019594650117973925842609576 153
UVM_INFO @ 10007294939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 97732108402812734655471417310742275023322702617650674055341195642888407974226 149
UVM_INFO @ 10010647001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 28342262943726719129181433310982662301163491229628036875044567718480193091084 140
UVM_INFO @ 10024025714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 64089633214605291030655552238784658750975238298180834919570797302179954486423 147
UVM_INFO @ 10006201600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 88364988062153931933652135056132991205389010903539463033406667767184113819116 151
UVM_INFO @ 10005562485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 32997245738419549124383945213191554190915138809057754788477963922156295019471 145
UVM_INFO @ 10013538583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 23569401164521351735358547041430490057518849276343395778260102186737629105474 146
UVM_INFO @ 10004306467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 9463195341070092831341217074060907238151801611701883366657276129333350614301 146
UVM_INFO @ 10017595643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 111872836252446639553249888407260808729623124824863891147250552907307679392582 152
UVM_INFO @ 10013555831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 95592561389567586267516885291987438987863235948275088239613401201679336050384 149
UVM_INFO @ 10055298134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 24 test runs
aes_control_fi 49557555047641370212499175923138444348108961634142538413625441338687752080359 143
UVM_INFO @ 10008426280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 113360653136897915703299345858425978564453371317018459943831231525031887089321 147
UVM_INFO @ 10007302492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 29324636748782379372441611694511745518222441578192422023464077376883293633451 146
UVM_INFO @ 10004699575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 104301893548330346263841651013574999244499940486013873011852449940839734847475 144
UVM_INFO @ 10029640673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 50166493529113648430044732705288391957524627717342912056025477670529151803062 141
UVM_INFO @ 10005390544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 6687689509997272658301457348780700593826558805107419956819001948443388163513 145
UVM_INFO @ 10040650956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 112064273982810006487942740599696065945274929111657845689762382894334246998296 154
UVM_INFO @ 10006689014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 46374476978359076950711891898673936502794235722671158238793700944244770594102 149
UVM_INFO @ 10005952672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 86857042934726299097744258401933880628764328723049572856912979579674326211396 146
UVM_INFO @ 10008028320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 71787310077529849025407254677443375657045620103283214397312699411651932538515 149
UVM_INFO @ 10008736564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 59647172366414659293480465285758550105874024649795594629027391290259030487894 147
UVM_INFO @ 10005563347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 55913179982954482498866045239886603420692849864030031155088584506536092109488 141
UVM_INFO @ 10005168960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 115609682519497836750601722038158729716400628828184253179764028917276407196274 145
UVM_INFO @ 10017864201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 76122034630108381614222683405719985461490222680521040733086202231866173919288 146
UVM_INFO @ 10042368269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 107915936008631074174773259679737922157861209097088299634865924150561828066149 146
UVM_INFO @ 10015991489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 7370105294312018085743439988435994081331829255089967019632380868878290638702 147
UVM_INFO @ 10005519527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 75822712752794348268284697115459017003211365699233328817044943636995230656618 144
UVM_INFO @ 10002325769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 45602741483496885055714382892773148621598794418340052250535363635369830420400 142
UVM_INFO @ 10020972108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 113929225813897025691295720754641221034806827675711124268857878073870312669210 148
UVM_INFO @ 10004103307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 30163431956804997699262879898781774949163195266390676820257105003927186450893 153
UVM_INFO @ 10008468943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 107798287601548927741044224119359351810509081158488961987184767554568454337013 140
UVM_INFO @ 10005652777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 89519086858331940651548529528753523841485915766446000639857843580042699228729 142
UVM_INFO @ 10003812923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 112306825867809074196860108372151802857311802255593667443080796164920662083767 153
UVM_INFO @ 10004332812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 115615693578252711429245689217935430445720911802214710059401229714502651585378 139
UVM_INFO @ 10009559811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 15 test runs
aes_control_fi 70566277230281233942084492241075680814412106251025649602422831997214723124940 None
aes_cipher_fi 45883754596600666701772213124250736722341108400921243018642521961799597973575 None
aes_control_fi 63070499254394091925716777411719061051316825714283989645745073587965331650684 None
aes_control_fi 37584518312540799609296817790665090279628814396075700402013231916819690879959 None
aes_cipher_fi 52990895883619057972063713645258553078568549857742412998919633511432986221246 None
aes_control_fi 109993800611464718492647995157130744904230979178278957983273906747124596989179 None
aes_control_fi 37782410971752528239362970931425416153229307385247047305776530717864481963090 None
aes_cipher_fi 79144507690770151636341136590506063495135136892237609658002248711310887419634 None
aes_cipher_fi 78709709246350901947326139922025813267442632874399845894754746282091723511457 None
aes_control_fi 90230584298812686053970050645836300988058553545036691350518441705293441733231 None
aes_cipher_fi 68283555157532641795142455059957513390183220362517132337979575045933366106007 None
aes_control_fi 25031392111013807663109233745470705892985847622441910354486413330403157754920 None
aes_control_fi 27317382474196159864426421673561748588583631561000328215220433285936709813123 None
aes_cipher_fi 12577160904004363613788392838745350702439384277531363107365961475468249802145 None
aes_cipher_fi 90082085125637662314571413088139628693597896378387930217394771349912565583565 None
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 11 test runs
aes_core_fi 17811584924005768917384460493101187910915071417825806032625692616577316516070 145
UVM_INFO @ 10019498676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 98289024504687608821132046356548830243428421068939114754512972323126474700611 147
UVM_INFO @ 10005357608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 72384389122308298339572450423921556208957589606805110690728157455999880363349 146
UVM_INFO @ 10018914272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 112270757799759962036869178083313749822094966303675136010599030087929017929991 140
UVM_INFO @ 10006411620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 101865579074662632485803443872278106470118917928951141283406002660589761230007 148
UVM_INFO @ 10009508879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 56511749185663391354484978935253106253079066790223071569379611228286269220010 141
UVM_INFO @ 10011606782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 34421042439906935207231861276375078020356846241527923308696747360564007356334 150
UVM_INFO @ 10009582239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 79133242963978112647520157700560368635813754100097622602344007772494541539321 150
UVM_INFO @ 10010583040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 111556889660624266224789942602807670423819204712668417119391571733737135146589 146
UVM_INFO @ 10006227161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 35256941749154573672971950079017973772746985385015624129040810368107127549150 153
UVM_INFO @ 10016110194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 25961214824991682494570032652955678067206524746516638460013130492505511309929 149
UVM_INFO @ 10003707316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 6 test runs
aes_stress_all_with_rand_reset 100703580903924739447534723302512454417910346126752451827438500841685897712638 281
UVM_INFO @ 449691151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 113484986259488082204280332551507023860207943223789511261748452647603769785574 287
UVM_INFO @ 254742448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 7194656163858399150342580089052903677998608116360313421364999096318654472094 1838
UVM_INFO @ 1445561638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 35926231221928999989915524576220557198231613626754492433781719598800714617965 510
UVM_INFO @ 142828916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 15338813090376267497295450251499886779398555575643067054147347114552487850711 891
UVM_INFO @ 289572702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 97831066282590455755357750419982999513353072354521620720819338779777289678032 631
UVM_INFO @ 4287272259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 3 test runs
aes_stress_all_with_rand_reset 26537238145224832498183156012972673808109303261687315743121841456785740095283 1129
UVM_INFO @ 5402692790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 109728016650974087210406375259494011506040826705493763984695829294998299840929 897
UVM_INFO @ 935461272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 38358101738359946101916992761727043132559282182906352384639931026347400762188 468
UVM_INFO @ 198667633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq__shadow_reg_errors.svh:336) [aes_common_vseq] ctrl_shadowed update_err alert timeout 2 test runs
aes_shadow_reg_errors_with_csr_rw 106590000740263388366477507848671354977009264197747689398788839118618270020422 106
UVM_INFO @ 10017037663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_shadow_reg_errors 93840098397417576163920049886658085388525186801016561284250447292429968265870 106
UVM_INFO @ 10058588530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: aes_reg_block_extended.ctrl_shadowed reset value: * 2 test runs
aes_shadow_reg_errors_with_csr_rw 76380305280893686218484880992449315376921795641747006674368872217154053563086 107
UVM_INFO @ 1363954502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_shadow_reg_errors 101660106481130915408681134670475499526791957023757932925876175018342233474864 106
UVM_INFO @ 19701995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:1031) virtual_sequencer [aes_stress_vseq] 1 test run
aes_stress_all_with_rand_reset 21879812928682634721383375431074106228118569384235322469587917149124978533533 161
Was able to clear FATAL ALERT without reset
---| Idle: 0
---| Stall: 0
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1136): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) 1 test run
aes_alert_reset 34279783097516737624189361374959703196953070234870978443673987023377295740711 1270
($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
|
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,1142): (time 4621742 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 4611104 PS)
UVM_ERROR @ 4621742 ps: (aes_core.sv:1136) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
aes_control_fi 36285807850985068220352233448986065894886277039048105836896443019937160809191 145
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---