| V1 |
|
98.44% |
| V2 |
|
86.49% |
| V2S |
|
100.00% |
| V3 |
|
88.05% |
| unmapped |
|
58.06% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_example_tests | 12 | 12 | 100.00 | |||
| chip_sw_example_flash | 210.440s | 3397.813us | 3 | 3 | 100.00 | |
| chip_sw_example_rom | 132.810s | 2697.529us | 3 | 3 | 100.00 | |
| chip_sw_example_manufacturer | 204.100s | 2793.517us | 3 | 3 | 100.00 | |
| chip_sw_example_concurrency | 193.320s | 3169.999us | 3 | 3 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| chip_csr_hw_reset | 362.620s | 7393.080us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| chip_csr_rw | 639.860s | 6621.490us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| chip_csr_bit_bash | 1130.830s | 12255.183us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| chip_csr_aliasing | 4709.760s | 33669.008us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 3 | 5 | 60.00 | |||
| chip_csr_mem_rw_with_rand_reset | 904.530s | 10334.455us | 3 | 5 | 60.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| chip_csr_aliasing | 4709.760s | 33669.008us | 1 | 1 | 100.00 | |
| chip_csr_rw | 639.860s | 6621.490us | 5 | 5 | 100.00 | |
| xbar_smoke | 50 | 50 | 100.00 | |||
| xbar_smoke | 12.450s | 257.028us | 50 | 50 | 100.00 | |
| chip_sw_gpio_out | 3 | 3 | 100.00 | |||
| chip_sw_gpio | 407.810s | 4243.562us | 3 | 3 | 100.00 | |
| chip_sw_gpio_in | 3 | 3 | 100.00 | |||
| chip_sw_gpio | 407.810s | 4243.562us | 3 | 3 | 100.00 | |
| chip_sw_gpio_irq | 3 | 3 | 100.00 | |||
| chip_sw_gpio | 407.810s | 4243.562us | 3 | 3 | 100.00 | |
| chip_sw_uart_tx_rx | 5 | 5 | 100.00 | |||
| chip_sw_uart_tx_rx | 482.510s | 4823.723us | 5 | 5 | 100.00 | |
| chip_sw_uart_rx_overflow | 20 | 20 | 100.00 | |||
| chip_sw_uart_tx_rx | 482.510s | 4823.723us | 5 | 5 | 100.00 | |
| chip_sw_uart_tx_rx_idx1 | 485.980s | 3980.403us | 5 | 5 | 100.00 | |
| chip_sw_uart_tx_rx_idx2 | 503.770s | 4542.949us | 5 | 5 | 100.00 | |
| chip_sw_uart_tx_rx_idx3 | 537.850s | 4472.625us | 5 | 5 | 100.00 | |
| chip_sw_uart_baud_rate | 20 | 20 | 100.00 | |||
| chip_sw_uart_rand_baudrate | 2280.560s | 12974.466us | 20 | 20 | 100.00 | |
| chip_sw_uart_tx_rx_alt_clk_freq | 10 | 10 | 100.00 | |||
| chip_sw_uart_tx_rx_alt_clk_freq | 2137.960s | 13712.079us | 5 | 5 | 100.00 | |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 1429.250s | 13789.752us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_pin_mux | 10 | 10 | 100.00 | |||
| chip_padctrl_attributes | 329.940s | 5624.741us | 10 | 10 | 100.00 | |
| chip_padctrl_attributes | 10 | 10 | 100.00 | |||
| chip_padctrl_attributes | 329.940s | 5624.741us | 10 | 10 | 100.00 | |
| chip_sw_sleep_pin_mio_dio_val | 1 | 3 | 33.33 | |||
| chip_sw_sleep_pin_mio_dio_val | 270.830s | 3122.831us | 1 | 3 | 33.33 | |
| chip_sw_sleep_pin_wake | 3 | 3 | 100.00 | |||
| chip_sw_sleep_pin_wake | 360.510s | 5696.612us | 3 | 3 | 100.00 | |
| chip_sw_sleep_pin_retention | 3 | 3 | 100.00 | |||
| chip_sw_sleep_pin_retention | 290.960s | 4399.847us | 3 | 3 | 100.00 | |
| chip_sw_tap_strap_sampling | 20 | 20 | 100.00 | |||
| chip_tap_straps_dev | 1201.460s | 14048.861us | 5 | 5 | 100.00 | |
| chip_tap_straps_testunlock0 | 477.930s | 6030.975us | 5 | 5 | 100.00 | |
| chip_tap_straps_rma | 507.490s | 6982.647us | 5 | 5 | 100.00 | |
| chip_tap_straps_prod | 668.360s | 8621.644us | 5 | 5 | 100.00 | |
| chip_sw_pattgen_ios | 3 | 3 | 100.00 | |||
| chip_sw_pattgen_ios | 219.100s | 3444.221us | 3 | 3 | 100.00 | |
| chip_sw_sleep_pwm_pulses | 3 | 3 | 100.00 | |||
| chip_sw_sleep_pwm_pulses | 1084.860s | 9939.752us | 3 | 3 | 100.00 | |
| chip_sw_data_integrity | 6 | 6 | 100.00 | |||
| chip_sw_data_integrity_escalation | 631.240s | 5518.863us | 6 | 6 | 100.00 | |
| chip_sw_instruction_integrity | 6 | 6 | 100.00 | |||
| chip_sw_data_integrity_escalation | 631.240s | 5518.863us | 6 | 6 | 100.00 | |
| chip_sw_ast_clk_outputs | 3 | 3 | 100.00 | |||
| chip_sw_ast_clk_outputs | 789.940s | 8123.443us | 3 | 3 | 100.00 | |
| chip_sw_ast_clk_rst_inputs | 0 | 3 | 0.00 | |||
| chip_sw_ast_clk_rst_inputs | 1927.930s | 13616.468us | 0 | 3 | 0.00 | |
| chip_sw_ast_sys_clk_jitter | 30 | 30 | 100.00 | |||
| chip_sw_flash_ctrl_ops_jitter_en | 491.360s | 4180.876us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_access_jitter_en | 741.370s | 6234.705us | 3 | 3 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 4867.110s | 19522.846us | 3 | 3 | 100.00 | |
| chip_sw_aes_enc_jitter_en | 233.050s | 2974.301us | 3 | 3 | 100.00 | |
| chip_sw_edn_entropy_reqs_jitter | 1003.200s | 7613.907us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_jitter_en | 239.890s | 3480.562us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation_jitter_en | 2135.890s | 14031.728us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 291.060s | 2937.081us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 593.950s | 6126.148us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_jitter | 216.100s | 3282.912us | 3 | 3 | 100.00 | |
| chip_sw_ast_usb_clk_calib | 1 | 1 | 100.00 | |||
| chip_sw_usb_ast_clk_calib | 232.350s | 3528.300us | 1 | 1 | 100.00 | |
| chip_sw_sensor_ctrl_ast_alerts | 7 | 8 | 87.50 | |||
| chip_sw_sensor_ctrl_alert | 742.240s | 8831.366us | 4 | 5 | 80.00 | |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 297.540s | 5603.751us | 3 | 3 | 100.00 | |
| chip_sw_sensor_ctrl_ast_status | 3 | 3 | 100.00 | |||
| chip_sw_sensor_ctrl_status | 199.190s | 3256.365us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 297.540s | 5603.751us | 3 | 3 | 100.00 | |
| chip_sw_smoketest | 51 | 51 | 100.00 | |||
| chip_sw_flash_scrambling_smoketest | 221.170s | 3055.604us | 3 | 3 | 100.00 | |
| chip_sw_aes_smoketest | 281.620s | 3082.294us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_smoketest | 298.870s | 3557.506us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_smoketest | 185.360s | 3035.927us | 3 | 3 | 100.00 | |
| chip_sw_csrng_smoketest | 212.260s | 2379.978us | 3 | 3 | 100.00 | |
| chip_sw_entropy_src_smoketest | 1337.630s | 8434.042us | 3 | 3 | 100.00 | |
| chip_sw_gpio_smoketest | 252.370s | 2608.112us | 3 | 3 | 100.00 | |
| chip_sw_hmac_smoketest | 274.930s | 3343.410us | 3 | 3 | 100.00 | |
| chip_sw_kmac_smoketest | 228.310s | 2588.447us | 3 | 3 | 100.00 | |
| chip_sw_otbn_smoketest | 1793.510s | 10878.865us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_smoketest | 432.720s | 6082.891us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_usbdev_smoketest | 407.660s | 6280.457us | 3 | 3 | 100.00 | |
| chip_sw_rv_plic_smoketest | 198.300s | 2961.922us | 3 | 3 | 100.00 | |
| chip_sw_rv_timer_smoketest | 228.980s | 3295.628us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_smoketest | 215.580s | 3169.277us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_smoketest | 232.480s | 3342.882us | 3 | 3 | 100.00 | |
| chip_sw_uart_smoketest | 264.660s | 3628.868us | 3 | 3 | 100.00 | |
| chip_sw_otp_smoketest | 3 | 3 | 100.00 | |||
| chip_sw_otp_ctrl_smoketest | 239.510s | 2690.011us | 3 | 3 | 100.00 | |
| chip_sw_rom_functests | 0 | 3 | 0.00 | |||
| rom_keymgr_functest | 567.910s | 4678.133us | 0 | 3 | 0.00 | |
| chip_sw_boot | 3 | 3 | 100.00 | |||
| chip_sw_uart_tx_rx_bootstrap | 12809.050s | 63034.634us | 3 | 3 | 100.00 | |
| chip_sw_secure_boot | 3 | 3 | 100.00 | |||
| rom_e2e_smoke | 3862.530s | 15382.294us | 3 | 3 | 100.00 | |
| chip_sw_rom_raw_unlock | 0 | 3 | 0.00 | |||
| rom_raw_unlock | 104.701s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_power_idle_load | 0 | 3 | 0.00 | |||
| chip_sw_power_idle_load | 297.710s | 3431.022us | 0 | 3 | 0.00 | |
| chip_sw_power_sleep_load | 0 | 3 | 0.00 | |||
| chip_sw_power_sleep_load | 250.500s | 2838.485us | 0 | 3 | 0.00 | |
| chip_sw_exit_test_unlocked_bootstrap | 3 | 3 | 100.00 | |||
| chip_sw_exit_test_unlocked_bootstrap | 12036.410s | 56220.960us | 3 | 3 | 100.00 | |
| chip_sw_inject_scramble_seed | 3 | 3 | 100.00 | |||
| chip_sw_inject_scramble_seed | 11282.460s | 57297.873us | 3 | 3 | 100.00 | |
| tl_d_oob_addr_access | 2 | 30 | 6.67 | |||
| chip_tl_errors | 368.910s | 4977.112us | 2 | 30 | 6.67 | |
| tl_d_illegal_access | 2 | 30 | 6.67 | |||
| chip_tl_errors | 368.910s | 4977.112us | 2 | 30 | 6.67 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| chip_csr_aliasing | 4709.760s | 33669.008us | 1 | 1 | 100.00 | |
| chip_same_csr_outstanding | 3674.160s | 30983.562us | 5 | 5 | 100.00 | |
| chip_csr_hw_reset | 362.620s | 7393.080us | 1 | 1 | 100.00 | |
| chip_csr_rw | 639.860s | 6621.490us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| chip_csr_aliasing | 4709.760s | 33669.008us | 1 | 1 | 100.00 | |
| chip_same_csr_outstanding | 3674.160s | 30983.562us | 5 | 5 | 100.00 | |
| chip_csr_hw_reset | 362.620s | 7393.080us | 1 | 1 | 100.00 | |
| chip_csr_rw | 639.860s | 6621.490us | 5 | 5 | 100.00 | |
| xbar_base_random_sequence | 50 | 50 | 100.00 | |||
| xbar_random | 94.490s | 2438.538us | 50 | 50 | 100.00 | |
| xbar_random_delay | 300 | 300 | 100.00 | |||
| xbar_smoke_zero_delays | 7.630s | 55.743us | 50 | 50 | 100.00 | |
| xbar_smoke_large_delays | 105.210s | 9744.056us | 50 | 50 | 100.00 | |
| xbar_smoke_slow_rsp | 115.150s | 7693.769us | 50 | 50 | 100.00 | |
| xbar_random_zero_delays | 46.030s | 572.852us | 50 | 50 | 100.00 | |
| xbar_random_large_delays | 418.250s | 50662.554us | 50 | 50 | 100.00 | |
| xbar_random_slow_rsp | 496.180s | 38997.027us | 50 | 50 | 100.00 | |
| xbar_unmapped_address | 100 | 100 | 100.00 | |||
| xbar_unmapped_addr | 57.420s | 1310.114us | 50 | 50 | 100.00 | |
| xbar_error_and_unmapped_addr | 52.810s | 1286.334us | 50 | 50 | 100.00 | |
| xbar_error_cases | 100 | 100 | 100.00 | |||
| xbar_error_random | 90.510s | 2461.516us | 50 | 50 | 100.00 | |
| xbar_error_and_unmapped_addr | 52.810s | 1286.334us | 50 | 50 | 100.00 | |
| xbar_all_access_same_device | 100 | 100 | 100.00 | |||
| xbar_access_same_device | 122.300s | 2996.897us | 50 | 50 | 100.00 | |
| xbar_access_same_device_slow_rsp | 1142.050s | 79918.069us | 50 | 50 | 100.00 | |
| xbar_all_hosts_use_same_source_id | 50 | 50 | 100.00 | |||
| xbar_same_source | 83.030s | 2711.039us | 50 | 50 | 100.00 | |
| xbar_stress_all | 100 | 100 | 100.00 | |||
| xbar_stress_all | 661.970s | 19738.488us | 50 | 50 | 100.00 | |
| xbar_stress_all_with_error | 450.870s | 15014.116us | 50 | 50 | 100.00 | |
| xbar_stress_with_reset | 100 | 100 | 100.00 | |||
| xbar_stress_all_with_rand_reset | 584.010s | 16714.969us | 50 | 50 | 100.00 | |
| xbar_stress_all_with_reset_error | 568.730s | 14330.617us | 50 | 50 | 100.00 | |
| rom_e2e_smoke | 3 | 3 | 100.00 | |||
| rom_e2e_smoke | 3862.530s | 15382.294us | 3 | 3 | 100.00 | |
| rom_e2e_shutdown_output | 3 | 3 | 100.00 | |||
| rom_e2e_shutdown_output | 3423.540s | 26114.610us | 3 | 3 | 100.00 | |
| rom_e2e_shutdown_exception_c | 3 | 3 | 100.00 | |||
| rom_e2e_shutdown_exception_c | 3732.800s | 15677.603us | 3 | 3 | 100.00 | |
| rom_e2e_boot_policy_valid | 0 | 15 | 0.00 | |||
| rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 30.756s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 11.839s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 9.555s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 9.954s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 9.799s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 129.967s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 9.051s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 9.873s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 11.226s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 11.027s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 60.156s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 12.522s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 12.019s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 10.872s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 11.487s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always | 0 | 15 | 0.00 | |||
| rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 30.900s | 10.160us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 34.710s | 10.340us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 19.700s | 10.260us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 31.740s | 10.160us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 27.580s | 10.140us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 22.260s | 10.300us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 35.400s | 10.140us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 32.030s | 10.180us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 21.060s | 10.340us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 23.320s | 10.140us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 32.480s | 10.380us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 33.920s | 10.400us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 25.910s | 10.180us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 33.660s | 10.140us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 28.310s | 10.380us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init | 0 | 15 | 0.00 | |||
| rom_e2e_asm_init_test_unlocked0 | 193.814s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_asm_init_dev | 11.955s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_asm_init_prod | 12.060s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_asm_init_prod_end | 11.980s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_asm_init_rma | 12.320s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_keymgr_init | 7 | 9 | 77.78 | |||
| rom_e2e_keymgr_init_rom_ext_meas | 7787.590s | 30973.627us | 3 | 3 | 100.00 | |
| rom_e2e_keymgr_init_rom_ext_no_meas | 8170.720s | 31359.224us | 3 | 3 | 100.00 | |
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 7196.620s | 29420.213us | 1 | 3 | 33.33 | |
| rom_e2e_static_critical | 3 | 3 | 100.00 | |||
| rom_e2e_static_critical | 3920.780s | 16673.512us | 3 | 3 | 100.00 | |
| chip_sw_adc_ctrl_debug_cable_irq | 0 | 3 | 0.00 | |||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 3600.172s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 0 | 3 | 0.00 | |||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 3600.172s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_aes_enc | 6 | 6 | 100.00 | |||
| chip_sw_aes_enc | 218.270s | 2369.260us | 3 | 3 | 100.00 | |
| chip_sw_aes_enc_jitter_en | 233.050s | 2974.301us | 3 | 3 | 100.00 | |
| chip_sw_aes_entropy | 3 | 3 | 100.00 | |||
| chip_sw_aes_entropy | 243.520s | 3369.913us | 3 | 3 | 100.00 | |
| chip_sw_aes_idle | 3 | 3 | 100.00 | |||
| chip_sw_aes_idle | 212.340s | 2565.798us | 3 | 3 | 100.00 | |
| chip_sw_aes_sideload | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_sideload_aes | 2021.850s | 12780.188us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_alerts | 0 | 3 | 0.00 | |||
| chip_sw_alert_test | 256.000s | 3701.670us | 0 | 3 | 0.00 | |
| chip_sw_alert_handler_escalations | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_escalation | 513.530s | 5443.101us | 3 | 3 | 100.00 | |
| chip_sw_all_escalation_resets | 96 | 100 | 96.00 | |||
| chip_sw_all_escalation_resets | 662.210s | 6149.641us | 96 | 100 | 96.00 | |
| chip_sw_alert_handler_irqs | 9 | 9 | 100.00 | |||
| chip_plic_all_irqs_0 | 743.020s | 5989.366us | 3 | 3 | 100.00 | |
| chip_plic_all_irqs_10 | 405.440s | 3518.044us | 3 | 3 | 100.00 | |
| chip_plic_all_irqs_20 | 505.300s | 4681.682us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_entropy | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_entropy | 287.050s | 3404.709us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_crashdump | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_alert_info | 1505.070s | 13279.809us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_ping_timeout | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_ping_timeout | 389.420s | 4977.280us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 0 | 90 | 0.00 | |||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 288.350s | 3389.162us | 0 | 90 | 0.00 | |
| chip_sw_alert_handler_lpg_sleep_mode_pings | 0 | 3 | 0.00 | |||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 14400.167s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_alert_handler_lpg_clock_off | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_lpg_clkoff | 1665.050s | 8877.606us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_lpg_reset_toggle | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_lpg_reset_toggle | 1590.600s | 8640.657us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_ping_ok | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_ping_ok | 1079.060s | 7885.913us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 13481.670s | 255907.126us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_wakeup_irq | 3 | 3 | 100.00 | |||
| chip_sw_aon_timer_irq | 448.320s | 4645.136us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_sleep_wakeup | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_smoketest | 432.720s | 6082.891us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_wdog_bark_irq | 3 | 3 | 100.00 | |||
| chip_sw_aon_timer_irq | 448.320s | 4645.136us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_wdog_bite_reset | 3 | 3 | 100.00 | |||
| chip_sw_aon_timer_wdog_bite_reset | 673.700s | 7950.534us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_sleep_wdog_bite_reset | 3 | 3 | 100.00 | |||
| chip_sw_aon_timer_wdog_bite_reset | 673.700s | 7950.534us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 5 | 5 | 100.00 | |||
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 403.020s | 7390.896us | 5 | 5 | 100.00 | |
| chip_sw_aon_timer_wdog_lc_escalate | 3 | 3 | 100.00 | |||
| chip_sw_aon_timer_wdog_lc_escalate | 522.430s | 4517.800us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_idle_trans | 12 | 12 | 100.00 | |||
| chip_sw_otbn_randomness | 781.820s | 6251.606us | 3 | 3 | 100.00 | |
| chip_sw_aes_idle | 212.340s | 2565.798us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_idle | 312.910s | 3904.520us | 3 | 3 | 100.00 | |
| chip_sw_kmac_idle | 217.680s | 3497.294us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_trans | 12 | 12 | 100.00 | |||
| chip_sw_clkmgr_off_aes_trans | 363.840s | 4108.805us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_hmac_trans | 441.780s | 5096.869us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_kmac_trans | 462.130s | 4202.909us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_otbn_trans | 446.740s | 5042.083us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_peri | 3 | 3 | 100.00 | |||
| chip_sw_clkmgr_off_peri | 1200.550s | 10460.519us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_div | 21 | 21 | 100.00 | |||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 518.940s | 4357.267us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 540.370s | 5639.053us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 564.460s | 4827.726us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 543.180s | 4318.696us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 562.340s | 4243.104us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 515.930s | 5067.100us | 3 | 3 | 100.00 | |
| chip_sw_ast_clk_outputs | 789.940s | 8123.443us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_lc | 3 | 3 | 100.00 | |||
| chip_sw_clkmgr_external_clk_src_for_lc | 520.200s | 7400.141us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw | 6 | 6 | 100.00 | |||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 564.460s | 4827.726us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 543.180s | 4318.696us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_jitter | 30 | 30 | 100.00 | |||
| chip_sw_flash_ctrl_ops_jitter_en | 491.360s | 4180.876us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_access_jitter_en | 741.370s | 6234.705us | 3 | 3 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 4867.110s | 19522.846us | 3 | 3 | 100.00 | |
| chip_sw_aes_enc_jitter_en | 233.050s | 2974.301us | 3 | 3 | 100.00 | |
| chip_sw_edn_entropy_reqs_jitter | 1003.200s | 7613.907us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_jitter_en | 239.890s | 3480.562us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation_jitter_en | 2135.890s | 14031.728us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 291.060s | 2937.081us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 593.950s | 6126.148us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_jitter | 216.100s | 3282.912us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_extended_range | 33 | 33 | 100.00 | |||
| chip_sw_clkmgr_jitter_reduced_freq | 229.760s | 3329.272us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 509.120s | 4829.877us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 866.820s | 7410.533us | 3 | 3 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 4859.610s | 24856.459us | 3 | 3 | 100.00 | |
| chip_sw_aes_enc_jitter_en_reduced_freq | 229.610s | 3235.974us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_jitter_en_reduced_freq | 274.120s | 3284.467us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 1462.910s | 12294.134us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 246.990s | 3216.227us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 584.330s | 6075.314us | 3 | 3 | 100.00 | |
| chip_sw_flash_init_reduced_freq | 1439.660s | 17798.353us | 3 | 3 | 100.00 | |
| chip_sw_csrng_edn_concurrency_reduced_freq | 22970.630s | 141410.961us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_deep_sleep_frequency | 3 | 3 | 100.00 | |||
| chip_sw_ast_clk_outputs | 789.940s | 8123.443us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_sleep_frequency | 3 | 3 | 100.00 | |||
| chip_sw_clkmgr_sleep_frequency | 517.370s | 4674.976us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_reset_frequency | 3 | 3 | 100.00 | |||
| chip_sw_clkmgr_reset_frequency | 375.020s | 3940.827us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_escalation_reset | 96 | 100 | 96.00 | |||
| chip_sw_all_escalation_resets | 662.210s | 6149.641us | 96 | 100 | 96.00 | |
| chip_sw_clkmgr_alert_handler_clock_enables | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_lpg_clkoff | 1665.050s | 8877.606us | 3 | 3 | 100.00 | |
| chip_sw_csrng_edn_cmd | 3 | 3 | 100.00 | |||
| chip_sw_entropy_src_csrng | 2890.690s | 24715.451us | 3 | 3 | 100.00 | |
| chip_sw_csrng_fuse_en_sw_app_read | 2 | 3 | 66.67 | |||
| chip_sw_csrng_fuse_en_sw_app_read_test | 456.060s | 4713.554us | 2 | 3 | 66.67 | |
| chip_sw_csrng_lc_hw_debug_en | 3 | 3 | 100.00 | |||
| chip_sw_csrng_lc_hw_debug_en_test | 668.650s | 7718.887us | 3 | 3 | 100.00 | |
| chip_sw_csrng_known_answer_tests | 3 | 3 | 100.00 | |||
| chip_sw_csrng_kat_test | 236.100s | 3047.976us | 3 | 3 | 100.00 | |
| chip_sw_edn_entropy_reqs | 16 | 16 | 100.00 | |||
| chip_sw_csrng_edn_concurrency | 5596.070s | 23063.509us | 10 | 10 | 100.00 | |
| chip_sw_entropy_src_ast_rng_req | 233.670s | 3061.932us | 3 | 3 | 100.00 | |
| chip_sw_edn_entropy_reqs | 1085.790s | 7013.334us | 3 | 3 | 100.00 | |
| chip_sw_entropy_src_ast_rng_req | 3 | 3 | 100.00 | |||
| chip_sw_entropy_src_ast_rng_req | 233.670s | 3061.932us | 3 | 3 | 100.00 | |
| chip_sw_entropy_src_csrng | 3 | 3 | 100.00 | |||
| chip_sw_entropy_src_csrng | 2890.690s | 24715.451us | 3 | 3 | 100.00 | |
| chip_sw_entropy_src_known_answer_tests | 3 | 3 | 100.00 | |||
| chip_sw_entropy_src_kat_test | 235.960s | 3238.276us | 3 | 3 | 100.00 | |
| chip_sw_flash_init | 3 | 3 | 100.00 | |||
| chip_sw_flash_init | 1597.320s | 24092.523us | 3 | 3 | 100.00 | |
| chip_sw_flash_host_access | 6 | 6 | 100.00 | |||
| chip_sw_flash_ctrl_access | 794.510s | 5861.240us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_access_jitter_en | 741.370s | 6234.705us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_ops | 6 | 6 | 100.00 | |||
| chip_sw_flash_ctrl_ops | 484.840s | 4489.030us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_ops_jitter_en | 491.360s | 4180.876us | 3 | 3 | 100.00 | |
| chip_sw_flash_rma_unlocked | 3 | 3 | 100.00 | |||
| chip_sw_flash_rma_unlocked | 4650.820s | 43340.539us | 3 | 3 | 100.00 | |
| chip_sw_flash_scramble | 3 | 3 | 100.00 | |||
| chip_sw_flash_init | 1597.320s | 24092.523us | 3 | 3 | 100.00 | |
| chip_sw_flash_idle_low_power | 3 | 3 | 100.00 | |||
| chip_sw_flash_ctrl_idle_low_power | 330.430s | 3883.018us | 3 | 3 | 100.00 | |
| chip_sw_flash_keymgr_seeds | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_key_derivation | 1961.420s | 12589.048us | 3 | 3 | 100.00 | |
| chip_sw_flash_lc_creator_seed_sw_rw_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 282.970s | 3681.415us | 0 | 3 | 0.00 | |
| chip_sw_flash_creator_seed_wipe_on_rma | 3 | 3 | 100.00 | |||
| chip_sw_flash_rma_unlocked | 4650.820s | 43340.539us | 3 | 3 | 100.00 | |
| chip_sw_flash_lc_owner_seed_sw_rw_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 282.970s | 3681.415us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_iso_part_sw_rd_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 282.970s | 3681.415us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_iso_part_sw_wr_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 282.970s | 3681.415us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_seed_hw_rd_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 282.970s | 3681.415us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_escalate_en | 96 | 100 | 96.00 | |||
| chip_sw_all_escalation_resets | 662.210s | 6149.641us | 96 | 100 | 96.00 | |
| chip_sw_flash_prim_tl_access | 3 | 3 | 100.00 | |||
| chip_prim_tl_access | 466.680s | 13142.436us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_clock_freqs | 3 | 3 | 100.00 | |||
| chip_sw_flash_ctrl_clock_freqs | 764.530s | 6239.748us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_escalation_reset | 3 | 3 | 100.00 | |||
| chip_sw_flash_crash_alert | 505.460s | 6098.283us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_write_clear | 3 | 3 | 100.00 | |||
| chip_sw_flash_crash_alert | 505.460s | 6098.283us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc | 6 | 6 | 100.00 | |||
| chip_sw_hmac_enc | 242.730s | 3319.144us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_jitter_en | 239.890s | 3480.562us | 3 | 3 | 100.00 | |
| chip_sw_hmac_idle | 3 | 3 | 100.00 | |||
| chip_sw_hmac_enc_idle | 312.910s | 3904.520us | 3 | 3 | 100.00 | |
| chip_sw_hmac_all_configurations | 3 | 3 | 100.00 | |||
| chip_sw_hmac_oneshot | 1381.020s | 8137.399us | 3 | 3 | 100.00 | |
| chip_sw_hmac_multistream_mode | 3 | 3 | 100.00 | |||
| chip_sw_hmac_multistream | 915.140s | 5775.967us | 3 | 3 | 100.00 | |
| chip_sw_i2c_host_tx_rx | 9 | 9 | 100.00 | |||
| chip_sw_i2c_host_tx_rx | 658.380s | 5487.356us | 3 | 3 | 100.00 | |
| chip_sw_i2c_host_tx_rx_idx1 | 617.350s | 5551.127us | 3 | 3 | 100.00 | |
| chip_sw_i2c_host_tx_rx_idx2 | 620.190s | 5968.201us | 3 | 3 | 100.00 | |
| chip_sw_i2c_device_tx_rx | 3 | 3 | 100.00 | |||
| chip_sw_i2c_device_tx_rx | 434.720s | 4679.126us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation | 6 | 6 | 100.00 | |||
| chip_sw_keymgr_key_derivation | 1961.420s | 12589.048us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation_jitter_en | 2135.890s | 14031.728us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_sideload_kmac | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_sideload_kmac | 1679.630s | 10092.258us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_sideload_aes | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_sideload_aes | 2021.850s | 12780.188us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_sideload_otbn | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_sideload_otbn | 3915.470s | 16847.260us | 3 | 3 | 100.00 | |
| chip_sw_kmac_enc | 9 | 9 | 100.00 | |||
| chip_sw_kmac_mode_cshake | 259.900s | 2908.851us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac | 251.340s | 3704.842us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 291.060s | 2937.081us | 3 | 3 | 100.00 | |
| chip_sw_kmac_app_keymgr | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_key_derivation | 1961.420s | 12589.048us | 3 | 3 | 100.00 | |
| chip_sw_kmac_app_lc | 14 | 15 | 93.33 | |||
| chip_sw_lc_ctrl_transition | 959.540s | 14505.334us | 14 | 15 | 93.33 | |
| chip_sw_kmac_app_rom | 3 | 3 | 100.00 | |||
| chip_sw_kmac_app_rom | 209.670s | 2529.185us | 3 | 3 | 100.00 | |
| chip_sw_kmac_entropy | 3 | 3 | 100.00 | |||
| chip_sw_kmac_entropy | 1485.130s | 8483.011us | 3 | 3 | 100.00 | |
| chip_sw_kmac_idle | 3 | 3 | 100.00 | |||
| chip_sw_kmac_idle | 217.680s | 3497.294us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_alert_handler_escalation | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_escalation | 513.530s | 5443.101us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_jtag_access | 15 | 15 | 100.00 | |||
| chip_tap_straps_dev | 1201.460s | 14048.861us | 5 | 5 | 100.00 | |
| chip_tap_straps_rma | 507.490s | 6982.647us | 5 | 5 | 100.00 | |
| chip_tap_straps_prod | 668.360s | 8621.644us | 5 | 5 | 100.00 | |
| chip_sw_lc_ctrl_otp_hw_cfg0 | 3 | 3 | 100.00 | |||
| chip_sw_lc_ctrl_otp_hw_cfg0 | 214.140s | 2714.363us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_init | 14 | 15 | 93.33 | |||
| chip_sw_lc_ctrl_transition | 959.540s | 14505.334us | 14 | 15 | 93.33 | |
| chip_sw_lc_ctrl_transitions | 14 | 15 | 93.33 | |||
| chip_sw_lc_ctrl_transition | 959.540s | 14505.334us | 14 | 15 | 93.33 | |
| chip_sw_lc_ctrl_kmac_req | 14 | 15 | 93.33 | |||
| chip_sw_lc_ctrl_transition | 959.540s | 14505.334us | 14 | 15 | 93.33 | |
| chip_sw_lc_ctrl_key_div | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_key_derivation_prod | 1654.480s | 10491.883us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_broadcast | 75 | 84 | 89.29 | |||
| chip_sw_flash_ctrl_lc_rw_en | 282.970s | 3681.415us | 0 | 3 | 0.00 | |
| chip_sw_flash_rma_unlocked | 4650.820s | 43340.539us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 324.260s | 3601.739us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_dev | 870.900s | 8044.124us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_prod | 687.710s | 7153.701us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_rma | 728.290s | 7611.605us | 0 | 3 | 0.00 | |
| chip_sw_lc_ctrl_transition | 959.540s | 14505.334us | 14 | 15 | 93.33 | |
| chip_sw_keymgr_key_derivation | 1961.420s | 12589.048us | 3 | 3 | 100.00 | |
| chip_sw_rom_ctrl_integrity_check | 503.720s | 9943.817us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_execution_main | 899.680s | 8567.584us | 3 | 3 | 100.00 | |
| chip_prim_tl_access | 466.680s | 13142.436us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_lc | 520.200s | 7400.141us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 518.940s | 4357.267us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 540.370s | 5639.053us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 564.460s | 4827.726us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 543.180s | 4318.696us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 562.340s | 4243.104us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 515.930s | 5067.100us | 3 | 3 | 100.00 | |
| chip_tap_straps_dev | 1201.460s | 14048.861us | 5 | 5 | 100.00 | |
| chip_tap_straps_rma | 507.490s | 6982.647us | 5 | 5 | 100.00 | |
| chip_tap_straps_prod | 668.360s | 8621.644us | 5 | 5 | 100.00 | |
| chip_rv_dm_lc_disabled | 413.050s | 14240.223us | 1 | 3 | 33.33 | |
| chip_lc_scrap | 5 | 6 | 83.33 | |||
| chip_sw_lc_ctrl_rma_to_scrap | 176.960s | 2872.513us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_raw_to_scrap | 105.810s | 3122.383us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_test_locked0_to_scrap | 114.330s | 2823.711us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_rand_to_scrap | 2419.190s | 27086.678us | 2 | 3 | 66.67 | |
| chip_lc_test_locked | 4 | 6 | 66.67 | |||
| chip_sw_lc_walkthrough_testunlocks | 2163.320s | 32990.081us | 3 | 3 | 100.00 | |
| chip_rv_dm_lc_disabled | 413.050s | 14240.223us | 1 | 3 | 33.33 | |
| chip_sw_lc_walkthrough | 6 | 15 | 40.00 | |||
| chip_sw_lc_walkthrough_dev | 959.300s | 11753.627us | 0 | 3 | 0.00 | |
| chip_sw_lc_walkthrough_prod | 925.220s | 10005.153us | 0 | 3 | 0.00 | |
| chip_sw_lc_walkthrough_prodend | 944.810s | 8792.746us | 3 | 3 | 100.00 | |
| chip_sw_lc_walkthrough_rma | 605.080s | 7846.973us | 0 | 3 | 0.00 | |
| chip_sw_lc_walkthrough_testunlocks | 2163.320s | 32990.081us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_volatile_raw_unlock | 5 | 9 | 55.56 | |||
| chip_sw_lc_ctrl_volatile_raw_unlock | 120.540s | 2444.892us | 2 | 3 | 66.67 | |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 125.130s | 2830.433us | 3 | 3 | 100.00 | |
| rom_volatile_raw_unlock | 97.166s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otbn_op | 6 | 6 | 100.00 | |||
| chip_sw_otbn_ecdsa_op_irq | 4840.600s | 16951.188us | 3 | 3 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 4867.110s | 19522.846us | 3 | 3 | 100.00 | |
| chip_sw_otbn_rnd_entropy | 3 | 3 | 100.00 | |||
| chip_sw_otbn_randomness | 781.820s | 6251.606us | 3 | 3 | 100.00 | |
| chip_sw_otbn_urnd_entropy | 3 | 3 | 100.00 | |||
| chip_sw_otbn_randomness | 781.820s | 6251.606us | 3 | 3 | 100.00 | |
| chip_sw_otbn_idle | 3 | 3 | 100.00 | |||
| chip_sw_otbn_randomness | 781.820s | 6251.606us | 3 | 3 | 100.00 | |
| chip_sw_otbn_mem_scramble | 3 | 3 | 100.00 | |||
| chip_sw_otbn_mem_scramble | 381.970s | 4012.730us | 3 | 3 | 100.00 | |
| chip_otp_ctrl_init | 14 | 15 | 93.33 | |||
| chip_sw_lc_ctrl_transition | 959.540s | 14505.334us | 14 | 15 | 93.33 | |
| chip_sw_otp_ctrl_keys | 15 | 15 | 100.00 | |||
| chip_sw_flash_init | 1597.320s | 24092.523us | 3 | 3 | 100.00 | |
| chip_sw_otbn_mem_scramble | 381.970s | 4012.730us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation | 1961.420s | 12589.048us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access | 494.530s | 4623.631us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_icache_invalidate | 235.300s | 3640.268us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_entropy | 15 | 15 | 100.00 | |||
| chip_sw_flash_init | 1597.320s | 24092.523us | 3 | 3 | 100.00 | |
| chip_sw_otbn_mem_scramble | 381.970s | 4012.730us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation | 1961.420s | 12589.048us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access | 494.530s | 4623.631us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_icache_invalidate | 235.300s | 3640.268us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_program | 14 | 15 | 93.33 | |||
| chip_sw_lc_ctrl_transition | 959.540s | 14505.334us | 14 | 15 | 93.33 | |
| chip_sw_otp_ctrl_program_error | 3 | 3 | 100.00 | |||
| chip_sw_lc_ctrl_program_error | 484.990s | 5634.379us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_hw_cfg0 | 3 | 3 | 100.00 | |||
| chip_sw_lc_ctrl_otp_hw_cfg0 | 214.140s | 2714.363us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals | 26 | 30 | 86.67 | |||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 324.260s | 3601.739us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_dev | 870.900s | 8044.124us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_prod | 687.710s | 7153.701us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_rma | 728.290s | 7611.605us | 0 | 3 | 0.00 | |
| chip_sw_lc_ctrl_transition | 959.540s | 14505.334us | 14 | 15 | 93.33 | |
| chip_prim_tl_access | 466.680s | 13142.436us | 3 | 3 | 100.00 | |
| chip_sw_otp_prim_tl_access | 3 | 3 | 100.00 | |||
| chip_prim_tl_access | 466.680s | 13142.436us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_dai_lock | 1 | 1 | 100.00 | |||
| chip_sw_otp_ctrl_dai_lock | 1100.680s | 7077.739us | 1 | 1 | 100.00 | |
| chip_sw_pwrmgr_external_full_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_full_aon_reset | 268.180s | 6842.832us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_random_sleep_all_wake_ups | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_random_sleep_all_wake_ups | 1427.680s | 23111.899us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_normal_sleep_all_wake_ups | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_normal_sleep_all_wake_ups | 401.440s | 7823.836us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_deep_sleep_por_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_deep_sleep_por_reset | 411.330s | 6715.404us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_normal_sleep_por_reset | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_normal_sleep_por_reset | 602.980s | 7895.145us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_deep_sleep_all_wake_ups | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_deep_sleep_all_wake_ups | 1437.530s | 25736.997us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 4 | 6 | 66.67 | |||
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 1223.310s | 14339.372us | 1 | 3 | 33.33 | |
| chip_sw_aon_timer_wdog_bite_reset | 673.700s | 7950.534us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 1341.180s | 12381.117us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_wdog_reset | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_wdog_reset | 466.730s | 5083.865us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_aon_power_glitch_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_full_aon_reset | 268.180s | 6842.832us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_main_power_glitch_reset | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_main_power_glitch_reset | 452.180s | 5382.335us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 1882.640s | 20123.640us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 440.070s | 7068.473us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_sleep_power_glitch_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_sleep_power_glitch_reset | 210.130s | 3562.007us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 1010.640s | 14510.778us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_sysrst_ctrl_reset | 6 | 6 | 100.00 | |||
| chip_sw_pwrmgr_sysrst_ctrl_reset | 940.020s | 8808.987us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_all_reset_reqs | 1369.340s | 11640.462us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_b2b_sleep_reset_req | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_b2b_sleep_reset_req | 2643.020s | 32130.482us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_sleep_disabled | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_sleep_disabled | 237.550s | 3430.402us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_escalation_reset | 96 | 100 | 96.00 | |||
| chip_sw_all_escalation_resets | 662.210s | 6149.641us | 96 | 100 | 96.00 | |
| chip_sw_rom_access | 3 | 3 | 100.00 | |||
| chip_sw_rom_ctrl_integrity_check | 503.720s | 9943.817us | 3 | 3 | 100.00 | |
| chip_sw_rom_ctrl_integrity_check | 3 | 3 | 100.00 | |||
| chip_sw_rom_ctrl_integrity_check | 503.720s | 9943.817us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_non_sys_reset_info | 9 | 12 | 75.00 | |||
| chip_sw_pwrmgr_all_reset_reqs | 1369.340s | 11640.462us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 1010.640s | 14510.778us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_wdog_reset | 466.730s | 5083.865us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_smoketest | 432.720s | 6082.891us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_sys_reset_info | 3 | 3 | 100.00 | |||
| chip_rv_dm_ndm_reset_req | 483.140s | 5813.911us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_cpu_info | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_cpu_info | 609.620s | 7297.437us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_sw_req_reset | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_sw_req | 414.560s | 4614.994us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_alert_info | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_alert_info | 1505.070s | 13279.809us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_sw_rst | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_sw_rst | 222.080s | 3057.566us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_escalation_reset | 96 | 100 | 96.00 | |||
| chip_sw_all_escalation_resets | 662.210s | 6149.641us | 96 | 100 | 96.00 | |
| chip_sw_rstmgr_alert_handler_reset_enables | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_lpg_reset_toggle | 1590.600s | 8640.657us | 3 | 3 | 100.00 | |
| chip_sw_nmi_irq | 3 | 3 | 100.00 | |||
| chip_sw_rv_core_ibex_nmi_irq | 636.290s | 5246.209us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_rnd | 3 | 3 | 100.00 | |||
| chip_sw_rv_core_ibex_rnd | 664.760s | 4942.451us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_address_translation | 3 | 3 | 100.00 | |||
| chip_sw_rv_core_ibex_address_translation | 251.610s | 3708.522us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_icache_scrambled_access | 3 | 3 | 100.00 | |||
| chip_sw_rv_core_ibex_icache_invalidate | 235.300s | 3640.268us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_fault_dump | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_cpu_info | 609.620s | 7297.437us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_double_fault | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_cpu_info | 609.620s | 7297.437us | 3 | 3 | 100.00 | |
| chip_jtag_csr_rw | 3 | 3 | 100.00 | |||
| chip_jtag_csr_rw | 1800.450s | 17862.275us | 3 | 3 | 100.00 | |
| chip_jtag_mem_access | 3 | 3 | 100.00 | |||
| chip_jtag_mem_access | 1329.300s | 13872.249us | 3 | 3 | 100.00 | |
| chip_rv_dm_ndm_reset_req | 3 | 3 | 100.00 | |||
| chip_rv_dm_ndm_reset_req | 483.140s | 5813.911us | 3 | 3 | 100.00 | |
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 0 | 3 | 0.00 | |||
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 250.420s | 2882.101us | 0 | 3 | 0.00 | |
| chip_rv_dm_access_after_wakeup | 3 | 3 | 100.00 | |||
| chip_sw_rv_dm_access_after_wakeup | 364.810s | 6257.519us | 3 | 3 | 100.00 | |
| chip_sw_rv_dm_jtag_tap_sel | 5 | 5 | 100.00 | |||
| chip_tap_straps_rma | 507.490s | 6982.647us | 5 | 5 | 100.00 | |
| chip_rv_dm_lc_disabled | 1 | 3 | 33.33 | |||
| chip_rv_dm_lc_disabled | 413.050s | 14240.223us | 1 | 3 | 33.33 | |
| chip_sw_plic_all_irqs | 9 | 9 | 100.00 | |||
| chip_plic_all_irqs_0 | 743.020s | 5989.366us | 3 | 3 | 100.00 | |
| chip_plic_all_irqs_10 | 405.440s | 3518.044us | 3 | 3 | 100.00 | |
| chip_plic_all_irqs_20 | 505.300s | 4681.682us | 3 | 3 | 100.00 | |
| chip_sw_plic_sw_irq | 3 | 3 | 100.00 | |||
| chip_sw_plic_sw_irq | 226.340s | 3219.542us | 3 | 3 | 100.00 | |
| chip_sw_timer | 3 | 3 | 100.00 | |||
| chip_sw_rv_timer_irq | 254.840s | 3509.292us | 3 | 3 | 100.00 | |
| chip_sw_spi_device_flash_mode | 3 | 3 | 100.00 | |||
| rom_e2e_smoke | 3862.530s | 15382.294us | 3 | 3 | 100.00 | |
| chip_sw_spi_device_pass_through | 3 | 3 | 100.00 | |||
| chip_sw_spi_device_pass_through | 469.900s | 6577.410us | 3 | 3 | 100.00 | |
| chip_sw_spi_device_pass_through_collision | 0 | 3 | 0.00 | |||
| chip_sw_spi_device_pass_through_collision | 270.430s | 3339.594us | 0 | 3 | 0.00 | |
| chip_sw_spi_device_tpm | 3 | 3 | 100.00 | |||
| chip_sw_spi_device_tpm | 329.130s | 3842.708us | 3 | 3 | 100.00 | |
| chip_sw_spi_host_tx_rx | 3 | 3 | 100.00 | |||
| chip_sw_spi_host_tx_rx | 254.860s | 2985.639us | 3 | 3 | 100.00 | |
| chip_sw_sram_scrambled_access | 6 | 6 | 100.00 | |||
| chip_sw_sram_ctrl_scrambled_access | 494.530s | 4623.631us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 593.950s | 6126.148us | 3 | 3 | 100.00 | |
| chip_sw_sleep_sram_ret_contents | 6 | 6 | 100.00 | |||
| chip_sw_sleep_sram_ret_contents_no_scramble | 661.840s | 9483.412us | 3 | 3 | 100.00 | |
| chip_sw_sleep_sram_ret_contents_scramble | 710.530s | 9510.600us | 3 | 3 | 100.00 | |
| chip_sw_sram_execution | 3 | 3 | 100.00 | |||
| chip_sw_sram_ctrl_execution_main | 899.680s | 8567.584us | 3 | 3 | 100.00 | |
| chip_sw_sram_lc_escalation | 102 | 106 | 96.23 | |||
| chip_sw_all_escalation_resets | 662.210s | 6149.641us | 96 | 100 | 96.00 | |
| chip_sw_data_integrity_escalation | 631.240s | 5518.863us | 6 | 6 | 100.00 | |
| chip_sw_sysrst_ctrl_reset | 6 | 6 | 100.00 | |||
| chip_sw_pwrmgr_sysrst_ctrl_reset | 940.020s | 8808.987us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_reset | 1411.710s | 23088.149us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_inputs | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_inputs | 231.470s | 3190.035us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_outputs | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_outputs | 344.480s | 3454.397us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_in_irq | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_in_irq | 442.620s | 4642.016us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_sleep_wakeup | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_reset | 1411.710s | 23088.149us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_sleep_reset | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_reset | 1411.710s | 23088.149us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_ec_rst_l | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_ec_rst_l | 3268.460s | 20176.590us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_flash_wp_l | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_ec_rst_l | 3268.460s | 20176.590us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_ulp_z3_wakeup | 3 | 6 | 50.00 | |||
| chip_sw_sysrst_ctrl_ulp_z3_wakeup | 475.320s | 6689.139us | 3 | 3 | 100.00 | |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 3600.172s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_usbdev_vbus | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_vbus | 187.120s | 2715.987us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_pullup | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_pullup | 277.070s | 3046.739us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_aon_pullup | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_aon_pullup | 420.050s | 3872.812us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_setup_rx | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_setuprx | 427.370s | 3607.154us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_config_host | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_config_host | 1420.940s | 8702.729us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_pincfg | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_pincfg | 7023.080s | 31561.023us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_tx_rx | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_dpi | 2459.240s | 12255.279us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_toggle_restore | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_toggle_restore | 261.220s | 3337.449us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_aes_masking_off | 3 | 3 | 100.00 | |||
| chip_sw_aes_masking_off | 282.660s | 2813.367us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_lockstep_glitch | 3 | 3 | 100.00 | |||
| chip_sw_rv_core_ibex_lockstep_glitch | 144.240s | 1993.139us | 3 | 3 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_coremark | 1 | 1 | 100.00 | |||
| chip_sw_coremark | 17336.640s | 71763.893us | 1 | 1 | 100.00 | |
| chip_sw_power_max_load | 3 | 3 | 100.00 | |||
| chip_sw_power_virus | 1454.890s | 6534.805us | 3 | 3 | 100.00 | |
| rom_e2e_debug | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_debug_test_unlocked0 | 262.610s | 3998.709us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_dev | 282.840s | 4533.187us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_rma | 547.960s | 5596.648us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject | 1 | 3 | 33.33 | |||
| rom_e2e_jtag_inject_test_unlocked0 | 95.790s | 1989.655us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject_dev | 349.360s | 6044.709us | 1 | 1 | 100.00 | |
| rom_e2e_jtag_inject_rma | 126.960s | 2641.139us | 0 | 1 | 0.00 | |
| rom_e2e_self_hash | 0 | 3 | 0.00 | |||
| rom_e2e_self_hash | 73.426s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_jitter_cycle_measurements | 0 | 3 | 0.00 | |||
| chip_sw_clkmgr_jitter_frequency | 381.320s | 3413.099us | 0 | 3 | 0.00 | |
| chip_sw_edn_boot_mode | 3 | 3 | 100.00 | |||
| chip_sw_edn_boot_mode | 441.490s | 3003.080us | 3 | 3 | 100.00 | |
| chip_sw_edn_auto_mode | 3 | 3 | 100.00 | |||
| chip_sw_edn_auto_mode | 1843.420s | 8561.621us | 3 | 3 | 100.00 | |
| chip_sw_edn_sw_mode | 3 | 3 | 100.00 | |||
| chip_sw_edn_sw_mode | 1518.310s | 9141.567us | 3 | 3 | 100.00 | |
| chip_sw_edn_kat | 3 | 3 | 100.00 | |||
| chip_sw_edn_kat | 328.390s | 2393.546us | 3 | 3 | 100.00 | |
| chip_sw_flash_memory_protection | 3 | 3 | 100.00 | |||
| chip_sw_flash_ctrl_mem_protection | 798.850s | 5521.580us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_vendor_test_csr_access | 3 | 3 | 100.00 | |||
| chip_sw_otp_ctrl_vendor_test_csr_access | 176.770s | 2667.236us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_escalation | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_escalation | 261.230s | 3649.085us | 0 | 1 | 0.00 | |
| chip_sw_sensor_ctrl_deep_sleep_wake_up | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 432.720s | 6105.926us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_usb_clk_disabled_when_active | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_usb_clk_disabled_when_active | 490.520s | 5900.028us | 3 | 3 | 100.00 | |
| chip_sw_all_resets | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_all_reset_reqs | 1369.340s | 11640.462us | 3 | 3 | 100.00 | |
| chip_rv_dm_perform_debug | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_debug_test_unlocked0 | 262.610s | 3998.709us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_dev | 282.840s | 4533.187us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_rma | 547.960s | 5596.648us | 0 | 1 | 0.00 | |
| chip_sw_rv_dm_access_after_hw_reset | 3 | 3 | 100.00 | |||
| chip_sw_rv_dm_access_after_escalation_reset | 575.450s | 5730.535us | 3 | 3 | 100.00 | |
| chip_sw_plic_alerts | 96 | 100 | 96.00 | |||
| chip_sw_all_escalation_resets | 662.210s | 6149.641us | 96 | 100 | 96.00 | |
| tick_configuration | 0 | 3 | 0.00 | |||
| chip_sw_rv_timer_systick_test | 7200.174s | 0.000us | 0 | 3 | 0.00 | |
| counter_wrap | 0 | 3 | 0.00 | |||
| chip_sw_rv_timer_systick_test | 7200.174s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_spi_device_output_when_disabled_or_sleeping | 3 | 3 | 100.00 | |||
| chip_sw_spi_device_pinmux_sleep_retention | 238.850s | 3606.008us | 3 | 3 | 100.00 | |
| chip_sw_uart_watermarks | 5 | 5 | 100.00 | |||
| chip_sw_uart_tx_rx | 482.510s | 4823.723us | 5 | 5 | 100.00 | |
| chip_sw_usbdev_stream | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_stream | 4080.860s | 18409.391us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 18 | 31 | 58.06 | |||
| chip_sival_flash_info_access | 250.030s | 2983.123us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_rst_cnsty_escalation | 27.800s | 10.260us | 0 | 3 | 0.00 | |
| chip_sw_otp_ctrl_rot_auth_config | 8.380s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_ecc_error_vendor_test | 239.180s | 2726.276us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_descrambling | 275.350s | 2718.802us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_lowpower_cancel | 300.370s | 3423.347us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_sleep_wake_5_bug | 13.245s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_ctrl_write_clear | 297.560s | 3454.762us | 3 | 3 | 100.00 | |
| ate_bootstrap_flash_erase | 879.980s | 10010.320us | 0 | 3 | 0.00 | |
| ate_bootstrap_one_frame | 9759.400s | 45047.182us | 3 | 3 | 100.00 | |
| ate_bootstrap_disjoint | 10800.172s | 0.000us | 0 | 3 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) | 90 test runs | |||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 102668229512389182317381184583675397075990214755479928975483713855900316838313 | 308 |
UVM_INFO @ 2499.275934 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 97043381271691154834437178710445656086450045264959769064190603056231185916074 | 308 |
UVM_INFO @ 2724.233880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 31558233951520602207403350586729006566789660310900879834847475834323634829636 | 308 |
UVM_INFO @ 2808.855510 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 26749152185383174589581530599428237963833776074207088139118547432041397269405 | 308 |
UVM_INFO @ 2850.075550 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 75815807574578669155630486427726328243805057106379569930203226858458159110716 | 308 |
UVM_INFO @ 2918.113120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 43373065474379971301879318407814190523196536564455317090852231727194214714779 | 308 |
UVM_INFO @ 2800.093598 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 28791193234164050158334667549868135279198063173254073665386403593435460175771 | 308 |
UVM_INFO @ 2504.208006 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 83234570417118400481119988924816227017573711158005745680760097360773368139278 | 308 |
UVM_INFO @ 2778.671612 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 19854458988873767681793981561205228743866339659400664539724538100403349949787 | 308 |
UVM_INFO @ 3335.024848 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 18685288810459651070856717661099830566437560355890583777495208988435764281103 | 308 |
UVM_INFO @ 2995.068787 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 96216020800815204947463286192725773454966368583018076384164824940980203427790 | 308 |
UVM_INFO @ 3132.423512 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 48109366115314848898553981167274315214209692828063376556727437527867154979500 | 308 |
UVM_INFO @ 2614.153504 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 9932075838493780950647895683679510441397286826357242197421959570586963369621 | 308 |
UVM_INFO @ 3147.649460 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 99185509243018390344384062302309203680820798913257859133333810813021030697492 | 308 |
UVM_INFO @ 3309.144134 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 30448894035321996619262572020396629987998315519883312712356017240379962319483 | 308 |
UVM_INFO @ 3220.824495 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 21087925697485596006965995159581881361786025956456443388482075902529614151826 | 308 |
UVM_INFO @ 3082.354770 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 12889100814894682958565325057655664884037681868965359560792758605061332886369 | 308 |
UVM_INFO @ 2941.126240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 16417452648586811265608638005696382012216046588428037135279530818663284260905 | 308 |
UVM_INFO @ 3329.541646 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 5041148060728379973601199506625019496185254968922084018171935807225796313006 | 308 |
UVM_INFO @ 2709.340327 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 76487834144303189963122023968865720269504878326301583039507696461951130194240 | 308 |
UVM_INFO @ 2650.388555 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 90954258452507790106660924536708055047495595411220469772494287721485824096700 | 308 |
UVM_INFO @ 2454.664352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 94870548070291936511414326443274417200087535377349783389374472140376329863457 | 308 |
UVM_INFO @ 2704.478472 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 85101699059544089855039722005256712384867885879935401624767811105234250760889 | 308 |
UVM_INFO @ 2808.813658 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 20471602801899499723118839588076168483459770080385371896367119019218992548527 | 308 |
UVM_INFO @ 2792.929006 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 97521296278169484276700801579840909962193423686581091011642444991065361040794 | 308 |
UVM_INFO @ 2293.635712 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 55122071532848292122247393026768559687946229220711464907863716943742214889929 | 308 |
UVM_INFO @ 3139.902355 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 12454722884394978468086078112998067810011990315162904771974165186918957820122 | 308 |
UVM_INFO @ 3081.546905 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 79638158649638766489514151894495081878644685193434577277262222176041469989724 | 308 |
UVM_INFO @ 3234.482408 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 1207083210987912276068604322727728956967415403144770442214610271584946569805 | 308 |
UVM_INFO @ 2679.431485 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 112449352050997251707641706821941828355857446234723806175939143408479915001082 | 308 |
UVM_INFO @ 2913.845272 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 104671686012123444321165129970373119735851041461178209428387748556244329424247 | 308 |
UVM_INFO @ 3206.049300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 29708190852134551915384721010403716366526540646926142749278394682676503967428 | 308 |
UVM_INFO @ 3215.525416 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 3340845590603405837191726328537996016670133029528190177496698587620476068693 | 308 |
UVM_INFO @ 3484.960080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 57127362267888319747083575914926553623494563687566049296974030381992931956097 | 308 |
UVM_INFO @ 2317.544323 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 16133929176375466032656189208485197292368236407681630106709368022856690402064 | 308 |
UVM_INFO @ 3329.938730 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 55541959060694288839599053456017559459111025978381004207964467692489376648003 | 308 |
UVM_INFO @ 3092.711585 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 13529764676394033255676238213416121185521670905828009281386668020892421528053 | 308 |
UVM_INFO @ 2887.917256 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 8015058049027270121605220183285790774964947339425170082232156065504468720886 | 308 |
UVM_INFO @ 2825.151425 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 71791443602942315566290012862695523441294585085262812379712740487195587475007 | 308 |
UVM_INFO @ 3289.898220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 14944823271578747512630690077330383832376658976083200485589672078901971323091 | 308 |
UVM_INFO @ 3125.638120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 97410711551589513653879351625997213713438204216411051643341983901733720057318 | 308 |
UVM_INFO @ 3085.527920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 101779425393052010278944371296103839083022469725717714121809745828975627472948 | 308 |
UVM_INFO @ 2805.692542 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 12850039260150567153673523345246681467971289172224258536850985569094442703223 | 308 |
UVM_INFO @ 3295.384185 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 19468701831225711121877024522638977434763178785780416892971631215662225776830 | 308 |
UVM_INFO @ 3241.340072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 54023018617201049160927624627474870173036957454881923789409321748406800228917 | 308 |
UVM_INFO @ 3356.862161 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 1061531866660204163867511607422698959084617467460204732142489434759334548492 | 308 |
UVM_INFO @ 3251.893064 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 60477914962082168040313201975021293277289424855701716343008529496944988799259 | 308 |
UVM_INFO @ 2901.981060 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 40550140482828319468436326841175413354285949949108346192819730988104071186000 | 308 |
UVM_INFO @ 3134.692304 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 50196155751151319047636391336039119619423211036342780844659488409111260916173 | 308 |
UVM_INFO @ 2548.045408 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 1599218757725600797664897152573524630063411129010110590458940551096531833620 | 308 |
UVM_INFO @ 2688.454968 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 19377510208406594780966507088838429392470565314535765003814800473328326071812 | 308 |
UVM_INFO @ 2552.588996 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 98610364831737656711680251404549462173869911205702668550687445593648841890728 | 308 |
UVM_INFO @ 2814.450870 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 75217787442009029852070268851858239770112030165005096839588294908232014718737 | 308 |
UVM_INFO @ 2775.391704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 15981128798244151398280488553325871209552590159477207950167467287901686562435 | 308 |
UVM_INFO @ 2523.272232 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 97547310174663845908583197205115167448696796525135942178236674206911631176690 | 308 |
UVM_INFO @ 3193.495444 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 45766259883451524093762883408266034869087319208550687065432659446369813430178 | 308 |
UVM_INFO @ 3116.635702 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 81464237943063638076450998114138790655584380669880132308579111508014930099345 | 308 |
UVM_INFO @ 2856.852424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 1742628790703439538304593708064853147627413123248249045809652660438679196519 | 308 |
UVM_INFO @ 2737.918479 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 103994919078081679471181112274236042909875833909342600880942878975693879402988 | 308 |
UVM_INFO @ 2888.506083 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 90172834750166210275307883649992394285320211528444211153007087344097058176943 | 308 |
UVM_INFO @ 3082.207724 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 23104828740696700808722915286383317446652943582749236604572178782757534372371 | 308 |
UVM_INFO @ 3155.310538 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 39165634334378962841410073282093773713187416115840784507462798765138582050953 | 308 |
UVM_INFO @ 3011.767487 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 104518254576034899673192647039795414216063789685122550875320656589904064172897 | 308 |
UVM_INFO @ 3442.235184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 47825741333899800267168003760970137049916714540368016298570373368713699732474 | 308 |
UVM_INFO @ 3036.485340 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 111913442078258030592072372663051475156846786262325338823741557879880950084499 | 308 |
UVM_INFO @ 3284.564436 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 83828085679301279285713460181283808303594485931114091937686310765783921647002 | 308 |
UVM_INFO @ 2788.589836 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 65857776141019090140784968053935175798135204459943875746583391169868034204754 | 308 |
UVM_INFO @ 3540.164360 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 79681084044761665920105848297172154090646740204827708683798653817864740954673 | 308 |
UVM_INFO @ 3540.715620 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 13845673321266430080804870812150073325621714178727057888827442392923909599702 | 308 |
UVM_INFO @ 3262.726902 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 92817739382314492193320963636167390963877049547150865937675425919613898359696 | 308 |
UVM_INFO @ 3080.079590 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 63770603499604211266474556781830438569559688565617897402528590487023182822587 | 308 |
UVM_INFO @ 3019.427350 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 76150535087422984192897584098310183028471236176300966425976634784010915683343 | 308 |
UVM_INFO @ 2648.631072 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 42516131900284288505773744580802689896489991629016436651499042608130858731549 | 308 |
UVM_INFO @ 3389.161598 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 23904639988356934428852903675519757652136632701438677570436934787089670661314 | 308 |
UVM_INFO @ 3266.000100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 100985908798811121185073698395929459020945009491977714614246631545502330250262 | 308 |
UVM_INFO @ 3282.285780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 16394741049247391434558062576358836793819628809710302681400691762996576207528 | 308 |
UVM_INFO @ 2785.095886 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 107633437864048522433900242677828210012113936730966476517501326173539876543374 | 308 |
UVM_INFO @ 2977.805040 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 81161687762130154915075506421547362586861472594032831590653790181797382783415 | 308 |
UVM_INFO @ 2794.044420 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 98664872448529076510434991600344348393105092763409246754444660808843444656501 | 308 |
UVM_INFO @ 3350.741713 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 81511620783183415342140670990843607579870124862479619645707163060214460674121 | 308 |
UVM_INFO @ 3720.589406 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 59444235955232819611105248863935990652360706240156713757990451400752953021129 | 308 |
UVM_INFO @ 2633.187664 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 110598751076759279039145090487437822329590326559416089529585447637065394396359 | 308 |
UVM_INFO @ 2797.664248 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 112114190356169033235194135156946039163735786589987006894951669262945596537899 | 308 |
UVM_INFO @ 2788.758448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 114839797888729033059094752038727932467082801467384920519183533814740284152445 | 308 |
UVM_INFO @ 3093.043395 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 34151976322392172382456617487007040660815841764279678857887911530417806040612 | 308 |
UVM_INFO @ 2470.094536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 40083354293533921491951087306365059158802757971047724819212510100889232381606 | 308 |
UVM_INFO @ 3550.138616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 25082168931884102746682420189316795281638124918852574806662631882347067976246 | 308 |
UVM_INFO @ 3660.507566 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 58331531010014293203584635030538700131121669738197313707561318911839301379232 | 308 |
UVM_INFO @ 3603.891344 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 12934834391485474329312402622055018403266493045205066293678191444597351511897 | 308 |
UVM_INFO @ 2360.986112 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 24522238108393599266272674770267606635722181564091048465261084270167322289465 | 308 |
UVM_INFO @ 3093.921931 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] | 42 test runs | |||
| chip_sw_pwrmgr_sleep_wake_5_bug | 68732627102886226397150368768908470618821508712125772388254525615940275026145 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 81012774747708901777964983383514667074276310763281105650667624481142557511558 | None |
Another command (pid=265232) is running. Waiting for it to complete on the server (server_pid=264628)...
Another command (pid=268327) is running. Waiting for it to complete on the server (server_pid=264628)...
Another command (pid=265623) is running. Waiting for it to complete on the server (server_pid=264628)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 86024086339271672336252838737457518188679462486555903153317685663923636048833 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 112975846379772969372236964758836017165773475616285394799055131388440820350996 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 99303961833203050288653135178053036097215711354286062642159852347556744533739 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 53425958522762112199885737675581978605167100742805940314261608734962659530673 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 71657423650275278042139432986310145729144914864597063548982733354477698669457 | None |
Another command (pid=269931) is running. Waiting for it to complete on the server (server_pid=264628)...
Another command (pid=275032) is running. Waiting for it to complete on the server (server_pid=264628)...
Another command (pid=271692) is running. Waiting for it to complete on the server (server_pid=264628)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 38525389209601415722749584272176614659737417843882788977601138627191357527003 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 73126424220797692862747640431654426047713218764321377023051443105727897226931 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 8606119937721520113924423459381941774924667254547169862956481212857263508955 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 102019443751700043087583060667696653097806720682371135813295519669477122050847 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 69067727737714758576218161104928346961018882656031215559850462524893381083313 | None |
---- STDERR ----
Another command (pid=267199) is running. Waiting for it to complete on the server (server_pid=264628)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 107077002541275032706144573568631199959124970437856026238385686070166613266740 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 2210793799963882932893519148510546324041613963807183769450697950666392181980 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 22552340809286953601169492088609831675219578960932007279390571916378323643895 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 14693782580548572009531152105731035862829322805965978790468193510961661431391 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_test_unlocked0 | 83728720048766339320056502225278468838999874399847498469851458964464227873883 | None |
Another command (pid=324957) is running. Waiting for it to complete on the server (server_pid=264628)...
Another command (pid=273337) is running. Waiting for it to complete on the server (server_pid=264628)...
Another command (pid=334177) is running. Waiting for it to complete on the server (server_pid=264628)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_dev | 86355258388160786189423047523834016843632734479141781764109940993069036762057 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod | 40664648465580848755107021728667115886757385140847580116857651002844446762209 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod_end | 62754430461034967454505025975210547175243001296510959248163118587080055422612 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_rma | 96492580125592079448601387665590447972409861829838427156240553053993078372255 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_volatile_raw_unlock | 68127623380488965397850445480567680550549480435408355932683504139969762689240 | None |
Another command (pid=273536) is running. Waiting for it to complete on the server (server_pid=264628)...
Another command (pid=294282) is running. Waiting for it to complete on the server (server_pid=264628)...
Another command (pid=269931) is running. Waiting for it to complete on the server (server_pid=264628)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_raw_unlock | 98619980925207438195793622092828375742545316664863344084202923538914929233737 | None |
Another command (pid=281003) is running. Waiting for it to complete on the server (server_pid=264628)...
Another command (pid=273536) is running. Waiting for it to complete on the server (server_pid=264628)...
Another command (pid=294282) is running. Waiting for it to complete on the server (server_pid=264628)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_self_hash | 3731583713293462933693077380156357647612805033337952872754920895723885518122 | None |
Another command (pid=270109) is running. Waiting for it to complete on the server (server_pid=264628)...
Another command (pid=267199) is running. Waiting for it to complete on the server (server_pid=264628)...
Another command (pid=268565) is running. Waiting for it to complete on the server (server_pid=264628)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_sleep_wake_5_bug | 72905381899954974172924985227440799088406493656791146117274138723489731578123 | None |
Another command (pid=4173795) is running. Waiting for it to complete on the server (server_pid=264628)...
Another command (pid=4174104) is running. Waiting for it to complete on the server (server_pid=264628)...
Another command (pid=4175030) is running. Waiting for it to complete on the server (server_pid=264628)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_test_unlocked0 | 73779334887433115141161489216002708354011898786071656990629414110108975325451 | None |
Another command (pid=267908) is running. Waiting for it to complete on the server (server_pid=264628)...
Another command (pid=285480) is running. Waiting for it to complete on the server (server_pid=264628)...
Another command (pid=295027) is running. Waiting for it to complete on the server (server_pid=264628)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_dev | 9300094351354242123647602913506993700508005784598841113815525476327052233249 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod | 104717024976778884101150506708601499900989797911181721204529302869314421264987 | None |
---- STDERR ----
Another command (pid=441332) is running. Waiting for it to complete on the server (server_pid=264628)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod_end | 41500184585475434940342699201308152062227064755181817671788199456750686448562 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_rma | 69807698243523401541284173746999269899424334128974450602150086684679881989045 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_volatile_raw_unlock | 25410358571800258196843554053825736935867138022944532959388518183133181333721 | None |
---- STDERR ----
Another command (pid=272856) is running. Waiting for it to complete on the server (server_pid=264628)...
Another command (pid=267908) is running. Waiting for it to complete on the server (server_pid=264628)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_raw_unlock | 104027697591756471475608668404630931672802553458047661097330541839746781888890 | None |
---- STDERR ----
Another command (pid=272856) is running. Waiting for it to complete on the server (server_pid=264628)...
Another command (pid=267908) is running. Waiting for it to complete on the server (server_pid=264628)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_self_hash | 108778161726759416813938989736950822001612968591244433769686053864739728750033 | None |
---- STDERR ----
Another command (pid=272856) is running. Waiting for it to complete on the server (server_pid=264628)...
Another command (pid=267908) is running. Waiting for it to complete on the server (server_pid=264628)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_sleep_wake_5_bug | 105338194348844588564530675067101003471865686997476078287985593559348398558458 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_test_unlocked0 | 65782823762814033804799742902386771136697196743047116201205378184753649274875 | None |
Another command (pid=280812) is running. Waiting for it to complete on the server (server_pid=264628)...
Another command (pid=303384) is running. Waiting for it to complete on the server (server_pid=264628)...
Another command (pid=270623) is running. Waiting for it to complete on the server (server_pid=264628)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_dev | 33667274574451469733643586433825352285562735374461916472679692258439871792725 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod | 86359801662600065415540941028088074004717368545996716960931172829007658057772 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod_end | 13504598117154416902730717259192483942553500652870693574521985334168177439137 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_rma | 10496479438300873452342933557439957948625633397453717510098332868739553653308 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_volatile_raw_unlock | 110741920108106803395592573941954722376680838765154545003826286986683385830189 | None |
Another command (pid=320581) is running. Waiting for it to complete on the server (server_pid=264628)...
Another command (pid=325108) is running. Waiting for it to complete on the server (server_pid=264628)...
Another command (pid=322629) is running. Waiting for it to complete on the server (server_pid=264628)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_raw_unlock | 114301352690290628508060328264925457528471544921760265618505849747517434313850 | None |
---- STDERR ----
Another command (pid=271692) is running. Waiting for it to complete on the server (server_pid=264628)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_self_hash | 90496442811028436279300184375836719101531383668467396616511804914054085855048 | None |
Another command (pid=286251) is running. Waiting for it to complete on the server (server_pid=264628)...
Another command (pid=303384) is running. Waiting for it to complete on the server (server_pid=264628)...
Another command (pid=270623) is running. Waiting for it to complete on the server (server_pid=264628)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). | 30 test runs | |||
| chip_tl_errors | 10395864446082489634781737885482855977955703715074133535865325474025262087314 | 217 |
TL item was: req: (cip_tl_seq_item@32628) { a_addr: 'h107a8 a_data: 'hb08a107 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h24 a_opcode: 'h4 a_user: 'h1a50e d_param: 'h0 d_source: 'h24 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2478.413545 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 60050512683399164481900169500096818061169765407326180891777757038036612370941 | 217 |
TL item was: req: (cip_tl_seq_item@33024) { a_addr: 'h10608 a_data: 'h60018bf9 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h18a3a d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2341.049800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 90925066385473178955497350573262359089367541162268412377596481906634645748176 | 217 |
TL item was: req: (cip_tl_seq_item@37712) { a_addr: 'h106b0 a_data: 'h67261a17 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h39 a_opcode: 'h4 a_user: 'h1927b d_param: 'h0 d_source: 'h39 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2359.809200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 33410477140073927473917174431273812870511294186234753021661542721547698468296 | 224 |
TL item was: req: (cip_tl_seq_item@32004) { a_addr: 'h10770 a_data: 'hfc46ba8 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h15 a_opcode: 'h4 a_user: 'h18d77 d_param: 'h0 d_source: 'h15 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2769.553240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 110852257607606126134381708300426339191439462593012837836061701458318880952625 | 217 |
TL item was: req: (cip_tl_seq_item@45180) { a_addr: 'h1059c a_data: 'ha27b8fdc a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h14 a_opcode: 'h4 a_user: 'h19edc d_param: 'h0 d_source: 'h14 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2219.011073 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 37131726130352857087588255255034977401145593426660242754256996857395857971674 | 217 |
TL item was: req: (cip_tl_seq_item@33050) { a_addr: 'h104e8 a_data: 'hc54a7ff9 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2d a_opcode: 'h4 a_user: 'h181c9 d_param: 'h0 d_source: 'h2d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2574.730120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 100008661421814283335915957697471551696870526177962655168961007333204687950202 | 224 |
TL item was: req: (cip_tl_seq_item@32438) { a_addr: 'h104f8 a_data: 'hc37fe655 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h23 a_opcode: 'h4 a_user: 'h1a51a d_param: 'h0 d_source: 'h23 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2234.800000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 42638574186726211791720436639374221825940789036348925790515270047116953214860 | 217 |
TL item was: req: (cip_tl_seq_item@31840) { a_addr: 'h107ec a_data: 'h1bd6c4f6 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h30 a_opcode: 'h4 a_user: 'h1816d d_param: 'h0 d_source: 'h30 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1985.354000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 77541190808164424499132807600710124929755586246539412833882779440233703567016 | 217 |
TL item was: req: (cip_tl_seq_item@33588) { a_addr: 'h10344 a_data: 'ha242cb99 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h12 a_opcode: 'h4 a_user: 'h1aedd d_param: 'h0 d_source: 'h12 d_data: 'hc51513 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd5b a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1810.511200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 87831353693517871555986517382496343193453126030373286553800691444860177097489 | 217 |
TL item was: req: (cip_tl_seq_item@39494) { a_addr: 'h104f0 a_data: 'h47b19872 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1 a_opcode: 'h4 a_user: 'h1b1ec d_param: 'h0 d_source: 'h1 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2645.341640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 52289613404022934760418719163370916942838457579927566509557521415565522720217 | 217 |
TL item was: req: (cip_tl_seq_item@37880) { a_addr: 'h105e8 a_data: 'h81375c8e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1d a_opcode: 'h4 a_user: 'h1869e d_param: 'h0 d_source: 'h1d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2349.573049 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 31665507993983722978253508107495666604178882305219430143538094502526192038831 | 217 |
TL item was: req: (cip_tl_seq_item@34126) { a_addr: 'h10544 a_data: 'he60027f0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h4 a_opcode: 'h4 a_user: 'h1b69b d_param: 'h0 d_source: 'h4 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2137.731220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 66587025808251428487644885404824861073014943888464797685912025226220758223610 | 217 |
TL item was: req: (cip_tl_seq_item@33800) { a_addr: 'h1055c a_data: 'h7d78b7d2 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h6 a_opcode: 'h4 a_user: 'h186d7 d_param: 'h0 d_source: 'h6 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2249.733976 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 58187292442579304458448986688608235283151176751291644994375769010643887771580 | 217 |
TL item was: req: (cip_tl_seq_item@33210) { a_addr: 'h10710 a_data: 'hd7ca06fc a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1 a_opcode: 'h4 a_user: 'h1bd1a d_param: 'h0 d_source: 'h1 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2496.085400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 80695932607900279181388669987148891085517049585682251557796721670761341558165 | 217 |
TL item was: req: (cip_tl_seq_item@33738) { a_addr: 'h106bc a_data: 'hfc1b5f8e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h5 a_opcode: 'h4 a_user: 'h18a76 d_param: 'h0 d_source: 'h5 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2116.005020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 74497003469206098963195812604058973034824068081902298441210830335226937174130 | 217 |
TL item was: req: (cip_tl_seq_item@32756) { a_addr: 'h10620 a_data: 'h1f724830 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h23 a_opcode: 'h4 a_user: 'h18647 d_param: 'h0 d_source: 'h23 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2178.508641 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 20523397761293599316974733821813201012402866799786034562865222418675895321887 | 217 |
TL item was: req: (cip_tl_seq_item@34022) { a_addr: 'h10650 a_data: 'h969fed7d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3c a_opcode: 'h4 a_user: 'h192d4 d_param: 'h0 d_source: 'h3c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2642.766700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 71877178509859371774500911620461759035038577961777951555214943400278476066442 | 217 |
TL item was: req: (cip_tl_seq_item@32548) { a_addr: 'h10440 a_data: 'hf6306ce5 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hf a_opcode: 'h4 a_user: 'h1bd63 d_param: 'h0 d_source: 'hf d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2681.465321 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 1436144684565193666626936745738432835509342851970609133962337808381827014709 | 217 |
TL item was: req: (cip_tl_seq_item@32734) { a_addr: 'h1078c a_data: 'h397822c9 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1e a_opcode: 'h4 a_user: 'h1b15b d_param: 'h0 d_source: 'h1e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1937.650503 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 66536538810061756187826186898797754556397314042758842297689943115841897014107 | 218 |
TL item was: req: (cip_tl_seq_item@134392) { a_addr: 'h10600 a_data: 'hcde79dcb a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3c a_opcode: 'h4 a_user: 'h19eb5 d_param: 'h0 d_source: 'h3c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3037.368760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 60657024348875239859161738679173362254660730731652362208677726595062405537725 | 217 |
TL item was: req: (cip_tl_seq_item@34972) { a_addr: 'h10678 a_data: 'h6d5f1c4e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h6 a_opcode: 'h4 a_user: 'h19ee4 d_param: 'h0 d_source: 'h6 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2435.311208 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 97001637239392257231410913299892532716093823527685045245236539061479509666253 | 217 |
TL item was: req: (cip_tl_seq_item@32700) { a_addr: 'h10728 a_data: 'hf85c499c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h14 a_opcode: 'h4 a_user: 'h195f9 d_param: 'h0 d_source: 'h14 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1892.707950 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 17278622666338740091448779401064811314585609146825838837379127322449627665753 | 217 |
TL item was: req: (cip_tl_seq_item@40804) { a_addr: 'h10300 a_data: 'ha7d25247 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3f a_opcode: 'h4 a_user: 'h18ac5 d_param: 'h0 d_source: 'h3f d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2422.130709 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 98453552407195735040170572728954362266765127656527186418732062019804078112210 | 217 |
TL item was: req: (cip_tl_seq_item@37094) { a_addr: 'h107b0 a_data: 'h9f58666 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3e a_opcode: 'h4 a_user: 'h1952b d_param: 'h0 d_source: 'h3e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2452.686658 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 67242956449863079297184979907425951840796789325057120930129948822625525548790 | 218 |
TL item was: req: (cip_tl_seq_item@148044) { a_addr: 'h1077c a_data: 'h41f2656a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h10 a_opcode: 'h4 a_user: 'h1951b d_param: 'h0 d_source: 'h10 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3639.708480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 114956453080386619623109820920186209778280361581658069456861648121231217000696 | 218 |
TL item was: req: (cip_tl_seq_item@137546) { a_addr: 'h10764 a_data: 'h4f86e19c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h26 a_opcode: 'h4 a_user: 'h1a546 d_param: 'h0 d_source: 'h26 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3324.631096 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 2306031301083865295079930527504090242043352258542015753212577559158600244835 | 217 |
TL item was: req: (cip_tl_seq_item@36002) { a_addr: 'h10630 a_data: 'h6c7ba523 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h7 a_opcode: 'h4 a_user: 'h1a2bf d_param: 'h0 d_source: 'h7 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2299.286532 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 36167621998460221896744478080169126674693901358093430561813753132830402092710 | 217 |
TL item was: req: (cip_tl_seq_item@36120) { a_addr: 'h10420 a_data: 'haf5a424d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h5 a_opcode: 'h4 a_user: 'h18d02 d_param: 'h0 d_source: 'h5 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2271.443440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 44625767753077597721062768237753088240455649781041755255803798258317586475659 | 217 |
TL item was: req: (cip_tl_seq_item@36314) { a_addr: 'h10734 a_data: 'h7b5a8945 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h9 a_opcode: 'h4 a_user: 'h1a904 d_param: 'h0 d_source: 'h9 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2494.001038 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 32891619717634379182941062571748183216718720463779936620411737344665147245280 | 218 |
TL item was: req: (cip_tl_seq_item@139276) { a_addr: 'h105e4 a_data: 'h70d2a852 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1a a_opcode: 'h4 a_user: 'h19e8f d_param: 'h0 d_source: 'h1a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3077.038864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | 12 test runs | |||
| chip_sw_rv_timer_systick_test | 85509064305928511003666412085092173299620407044955311630422262580737522910860 | None | ||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 103629773991147264887106412669269633693795077591984305224736255497026012009761 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 30241210927235726046914145742368238871036568471776345710819745227514068019549 | None | ||
| ate_bootstrap_disjoint | 114074891947075541172812773900485372001115311115174527044981136369959702075685 | None | ||
| chip_sw_rv_timer_systick_test | 32047771331737193532965816706452993816495549389580942821537728068366013913740 | None | ||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 99766131792665798453032918617562102077145795268391141421655433790819740646443 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 12875175298654187240427025833335531393964612146281264736069484723222621289826 | None | ||
| ate_bootstrap_disjoint | 94959112855118273162731592636999324889342019403612122719681487101942034046004 | None | ||
| chip_sw_rv_timer_systick_test | 37995170747183349627534529602628177038275071141233881305171263485581872814822 | None | ||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 94910557052508656355970474789881778784143323673216582074718779662886703352470 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 77818858276169229137048753133778049547210349369398675569278062902009889388242 | None | ||
| ate_bootstrap_disjoint | 17716531405127310435824914771104430307736831502556931447638178300380887741315 | None | ||
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected | 9 test runs | |||
| chip_sw_lc_walkthrough_dev | 66130894401394279244807493296766212293358491170153586613770545511015403030087 | 369 |
UVM_INFO @ 11753.627390 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_prod | 80595324008560448376474318090274356615633105685605510188167074702470779241639 | 369 |
UVM_INFO @ 8811.811075 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_rma | 73700066846126721774274432291569858464450131096409182945057256769671118186063 | 341 |
UVM_INFO @ 7846.973417 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_dev | 73345712659635292466598765189912433638166737923883339210732003317357057183460 | 369 |
UVM_INFO @ 10436.076705 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_prod | 13168830727748605887597197801175463132940490290754221333887080723951536433285 | 369 |
UVM_INFO @ 10005.152712 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_rma | 62308920360653495645498660791662895076016289138983254133362510618922720632796 | 341 |
UVM_INFO @ 6790.012697 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_dev | 14739364848973117085287457713116847878247246554915526094185425520205532322207 | 369 |
UVM_INFO @ 9938.872148 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_prod | 89733409760174612002300865704337375984633468737989776792258537443981827404681 | 369 |
UVM_INFO @ 7669.102483 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_rma | 3595140814045075286263046011431210526702131149614856059370572384523857727788 | 341 |
UVM_INFO @ 6843.191718 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '(rstreqs[*] && (reset_cause == HwReq))' | 9 test runs | |||
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 47503585822788282335599399853583448772596202978033123559581397860015256912537 | 344 |
UVM_ERROR @ 12991.484000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 12991.484000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_deep_sleep_por_reset | 52964663940540307865391449503622671246706056093762837842567882892435982119086 | 325 |
UVM_ERROR @ 7596.076000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7596.076000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 89422028083545268337100717177391659081215275148142443536699743002674893016429 | 330 |
UVM_ERROR @ 8932.151500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8932.151500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 62057193734382622343444493459322068066147275266362705926787842846136161447557 | 344 |
UVM_ERROR @ 12240.473500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 12240.473500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_deep_sleep_por_reset | 27325622995971285093183983895693308311330248284699533885385576896288714496565 | 325 |
UVM_ERROR @ 6715.404000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6715.404000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 95273152984078955935659645457269197022295715664832701113788951653383860373136 | 380 |
UVM_ERROR @ 20123.640000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 20123.640000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 40752171334364632009722441525465504425267067657868730969304334015695611260253 | 344 |
UVM_ERROR @ 14510.777500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 14510.777500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 114374684096704289445672623701309107157345007706741432889285341884053235919912 | 327 |
UVM_ERROR @ 9627.248000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9627.248000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_deep_sleep_por_reset | 42697664838448063812745927866838768548994291161948901559157267863490865709352 | 325 |
UVM_ERROR @ 7603.948000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7603.948000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Error-[NOA] Null object access | 8 test runs | |||
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 55553955056786570132093410962584779551500560468846239201833385253008658262628 | 327 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| rom_e2e_jtag_debug_test_unlocked0 | 80043801142734411181729018216459006046778104406172976245702532906474922734909 | 319 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| rom_e2e_jtag_debug_dev | 44863008421853064607599984844261275370634054280034053252051751800530660839956 | 319 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| rom_e2e_jtag_debug_rma | 99548385451831482807024819757791236783285740540579227765327249606014275089521 | 352 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| rom_e2e_jtag_inject_test_unlocked0 | 86878186267861800364942296155139217072728833783445691421484375882202586507307 | 303 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| rom_e2e_jtag_inject_rma | 103056686878811419571923779436488278095756816410481085838461075217642357514802 | 303 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 44038347699721049892754837715003942248205500492834382508829841325979700503278 | 327 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 107584554958921901888170878392541134636651810798992767974034336024741462019329 | 327 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode | 6 test runs | |||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 75926986175046285331912266035386908230430684777057605678248709309524492710933 | 367 |
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 6610526673681403135445902116843141747185078270807043928599922818113155324358 | 364 |
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 73178055391366432789355308395193643376470123708365399920631691805066396843961 | 368 |
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 59261114522991881208165229959064178093661570516321740258591146337004209943319 | 328 |
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 27290657502276049237906586167551682659636046530772549938207839294472813872276 | 328 |
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 7198497273429347579808303594633106254185269388660830140448504889273204810715 | 325 |
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' | 4 test runs | |||
| chip_sw_pwrmgr_sleep_power_glitch_reset | 89306777661633622461096406350827826180576725807045187853550790981936255449907 | 313 |
UVM_ERROR @ 2998.581436 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 2998.581436 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_sleep_power_glitch_reset | 64782067435015445793218009243558170503158549648524557850539711449717178035031 | 313 |
UVM_ERROR @ 3562.007220 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3562.007220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_sleep_power_glitch_reset | 94704257388074353361561007848187641793193115723896956694220067694319393498689 | 313 |
UVM_ERROR @ 2529.893176 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 2529.893176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 5990605640471742852101511805000703121509782539514362426476407725481721742462 | 343 |
UVM_ERROR @ 12228.863201 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 12228.863201 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr_aon.u_d0_spi_host*.leaf_rst_path | 3 test runs | |||
| chip_sw_rstmgr_rst_cnsty_escalation | 54078346385676851963447329773018659026827866819194066715384460193427337009779 | 301 |
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_rstmgr_rst_cnsty_escalation | 4565563956472788004169249180868283252182103201455935779907917540095007001550 | 301 |
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_rstmgr_rst_cnsty_escalation | 51953565124337212137940173093396953288914368244963067441262109660354613105905 | 301 |
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected | 3 test runs | |||
| chip_sw_flash_ctrl_lc_rw_en | 5847367548504995797104377832275133034649931357063088068452566241194256995309 | 309 |
UVM_INFO @ 3681.414570 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_flash_ctrl_lc_rw_en | 9848245493771171858562320403715933582437696995541408620338437329036141634193 | 309 |
UVM_INFO @ 2764.626808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_flash_ctrl_lc_rw_en | 53019597886371389138288552917440577894276461231549887731910301398289419314849 | 309 |
UVM_INFO @ 3336.092664 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * | 3 test runs | |||
| chip_sw_otp_ctrl_lc_signals_rma | 104348295700189095020827220514787206390467439177808086559278266503044715242815 | 342 |
UVM_INFO @ 7611.604909 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_otp_ctrl_lc_signals_rma | 100848988175785779475454672355048982346248359429486339766594812307957607228749 | 342 |
UVM_INFO @ 5817.532492 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_otp_ctrl_lc_signals_rma | 2306140927157486556877010084732200288134417536973143490777636128626846964606 | 342 |
UVM_INFO @ 7193.279961 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' | 3 test runs | |||
| chip_sw_otp_ctrl_escalation | 69587263045831389993302923748835887358420610123224790849935807170971157765990 | 316 |
UVM_ERROR @ 3649.084614 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3649.084614 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_csrng_fuse_en_sw_app_read_test | 56521937126536743284768118132511368829450173756328559693391179233335795949374 | 312 |
UVM_ERROR @ 2787.743240 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2787.743240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 69499231212153932007243661963572496757732014126080135987680842182071080483989 | 317 |
UVM_ERROR @ 2401.367658 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2401.367658 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '((~rst_ni) === (~seed_en_q))' | 3 test runs | |||
| chip_sw_pwrmgr_full_aon_reset | 54990714509654615599926544841245109034503105367874940487928305410170423929114 | 303 |
UVM_ERROR @ 2350.056760 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 2350.056760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_full_aon_reset | 55758627855702707064827045720956536080887248791500857125763250758228298259701 | 322 |
UVM_ERROR @ 6882.552245 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 6882.552245 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_full_aon_reset | 74343892904878171607697221125550696082232404346125400457796288478686509061426 | 322 |
UVM_ERROR @ 6842.831781 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 6842.831781 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected | 3 test runs | |||
| chip_sw_clkmgr_jitter_frequency | 115465534424174365636767118161784566607210615622114421585980072981087350186643 | 343 |
UVM_INFO @ 3616.406356 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_clkmgr_jitter_frequency | 68686044371556297878762666773817881279427419235320956453079885378016039035688 | 343 |
UVM_INFO @ 3438.542570 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_clkmgr_jitter_frequency | 102548689722121455331298659104066097748130363845392033011924867238441530636100 | 343 |
UVM_INFO @ 3413.098867 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * | 3 test runs | |||
| chip_sw_power_idle_load | 111432159938528775565220444986203211492181436464025471641824927355954281319151 | 312 |
UVM_INFO @ 3203.055000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_power_idle_load | 78982051765074464869037609801167399794520779168508324965051285412508764366890 | 312 |
UVM_INFO @ 3772.261000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_power_idle_load | 26320564685846092458341156803936018781980312223577496588341283100708767226047 | 312 |
UVM_INFO @ 3431.022000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * | 3 test runs | |||
| chip_sw_power_sleep_load | 56544053545766044871381015550100121751615124470295404247766900915168690919491 | 318 |
UVM_INFO @ 3447.252000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_power_sleep_load | 111448249838836535175146507144251867345097086326258439551555759324862811162886 | 318 |
UVM_INFO @ 3143.355000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_power_sleep_load | 47208233594119361761232837322878182246416578315654073668973360552209854184172 | 318 |
UVM_INFO @ 2838.485000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * | 3 test runs | |||
| chip_sw_ast_clk_rst_inputs | 32297401519168938667673053091479846365712919510991606146625771515758687007614 | 327 |
UVM_INFO @ 9438.620090 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_ast_clk_rst_inputs | 55639158317664574687455227398876114111457993170335186484061589134139488843119 | 327 |
UVM_INFO @ 13616.467968 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_ast_clk_rst_inputs | 47742074645172253254143792558837731222274406489695523989932980197035180150551 | 327 |
UVM_INFO @ 13513.898555 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) | 3 test runs | |||
| ate_bootstrap_flash_erase | 108048189096639545066608733692018430259942285875723441555029933964964582123111 | 272 |
UVM_INFO @ 10010.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| ate_bootstrap_flash_erase | 29586981422563210079080705678212203589689343388829835003976718173851498795046 | 272 |
UVM_INFO @ 10010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| ate_bootstrap_flash_erase | 25818119389472167735995196150650366771065531629233409738953358088043503057166 | 272 |
UVM_INFO @ 10010.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode | 3 test runs | |||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 38243254569297290398148036937444809334243504809874270049474698475498147729454 | 326 |
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 68886226624380950114193276020970372516627481093694448382361572869301886361675 | 326 |
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 111719957288229860582268733094957268921968100000927043837862832509783660354650 | 325 |
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '$stable(key_data_i)' | 3 test runs | |||
| rom_keymgr_functest | 99137245224611428049316030567088289238296091789703660760407218915773435877081 | 327 |
UVM_ERROR @ 4678.133400 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4678.133400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_keymgr_functest | 78357684763574712744922902806284623342359789812911068009964274038667776496192 | 327 |
UVM_ERROR @ 6321.991984 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 6321.991984 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_keymgr_functest | 51109015180024662180948979769985257561032182292419306620470124455260862317404 | 327 |
UVM_ERROR @ 3537.889660 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 3537.889660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] | 2 test runs | |||
| chip_sw_sleep_pin_mio_dio_val | 96718089916391123406232311846595823047792051150535048413625340565907023895350 | 451 |
UVM_INFO @ 2655.806000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_sleep_pin_mio_dio_val | 77948880760437003626232485357422604180255466564918140827004179796179057148798 | 451 |
UVM_INFO @ 3360.768500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty | 2 test runs | |||
| chip_sw_spi_device_pass_through_collision | 97224810908363496484388554536945776830310844827674838244823706329161596435980 | 327 |
UVM_INFO @ 2919.613297 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_spi_device_pass_through_collision | 67534856428464053485575397507079458991815388182187270025192357008632368355917 | 327 |
UVM_INFO @ 3339.593998 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch | 2 test runs | |||
| chip_rv_dm_lc_disabled | 17109825997097823730701849564160438025833929283851872218029215304688985585378 | 215 |
UVM_INFO @ 2267.780718 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_rv_dm_lc_disabled | 85286339065836671542258821098011212724976045816490439465103577219199448922271 | 215 |
UVM_INFO @ 2904.562268 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode | 2 test runs | |||
| rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 84312919755862403198209453081517226533656592340117698353307131482657083742280 | 363 |
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 28310654157390301049113939837831539212185350120878590162257294354875243413885 | 326 |
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode | 2 test runs | |||
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 55966003223757027471713761414760830575156003414141992880587035566830363791810 | 367 |
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 85538156573930966255982308178915897509608304634092305674990016738108318762180 | 325 |
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * | 2 test runs | |||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 54162968256860837529564386224088951506881127368760138891264880053079627191869 | 319 |
UVM_INFO @ 15954.142800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 11178252355506682817400435683470679467090946423459205156177656323121247686249 | 319 |
UVM_INFO @ 16025.635295 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (cip_base_vseq.sv:923) virtual_sequencer [chip_sw_all_escalation_resets_vseq] Alert usbdev_fatal_fault fired unexpectedly. | 2 test runs | |||
| chip_sw_all_escalation_resets | 22272325609792928900682744497591050631387698614178367508042111868813293516950 | 316 |
UVM_INFO @ 3160.390152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 38081785979004663913051242546943211509267962670411768714473411554103023916193 | 316 |
UVM_INFO @ 3164.868966 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode | 1 test run | |||
| chip_sw_otp_ctrl_rot_auth_config | 17710900582547831006368926510879314574885408409908441300252706896359960245633 | 282 |
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '(pend_req[h2d.a_source].pend == *)' | 1 test run | |||
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 10109360658611025906325952986223702640462879679814760560912001403135188287282 | 341 |
UVM_ERROR @ 9858.095280 us: (tlul_assert.sv:314) [ASSERT FAILED] pendingReqPerSrc_M
UVM_INFO @ 9858.095280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:367)] CHECK-fail: Expect alert *! | 1 test run | |||
| chip_sw_alert_test | 2288361090187632775216629977786117250416846433732499432987317444848784215703 | 307 |
UVM_INFO @ 2665.083657 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode | 1 test run | |||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 93144005202007992064167094785641194488836216939982864672442255728013322428114 | 326 |
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode | 1 test run | |||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 85323771696885476420777171186940979752827846533502654299536893539523650685211 | 328 |
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch | 1 test run | |||
| chip_sw_spi_device_pass_through_collision | 109922661265430390990697453052372820272313986216839810728612227248132711203067 | 329 |
host_rsp:
-------------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------------
|
|
| UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched! | 1 test run | |||
| chip_sw_lc_ctrl_rand_to_scrap | 112770781651501871369207909685476498799763362504359117188479762689413993911486 | 313 |
UVM_INFO @ 27086.677879 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:412)] CHECK-fail: Expect alert *! | 1 test run | |||
| chip_sw_alert_test | 60665496072139613642446922369493027902868175750443995922806441229673042851478 | 307 |
UVM_INFO @ 3701.670372 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '(reset_cause == HwReq)' | 1 test run | |||
| chip_sw_sensor_ctrl_alert | 82918655759636915076798868664646842070326410653275133549145030765250534472040 | 316 |
UVM_ERROR @ 2733.897800 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
UVM_INFO @ 2733.897800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (chip_sw_base_vseq.sv:945) [chip_sw_lc_volatile_raw_unlock_vseq] Check failed (!(transition_ctrl & (* << *))) VOLATILE_RAW_UNLOCK is not expected to be supported by this top-level. Check the SecVolatileRawUnlockEn parameter configuration. | 1 test run | |||
| chip_sw_lc_ctrl_volatile_raw_unlock | 93197166734630022592075721924926649197427662376563600166933810360996596570545 | 307 |
UVM_INFO @ 2509.667630 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert *! | 1 test run | |||
| chip_sw_alert_test | 12755870830526274143758081562170161631304514115259714550289804862764605396484 | 307 |
UVM_INFO @ 2999.091473 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_ctrl_transition_vseq] max attempt reached to get lc status LcExtClockSwitched! | 1 test run | |||
| chip_sw_lc_ctrl_transition | 32206305737776946989309857545622382370014433676846398705595603431568865665106 | 305 |
UVM_INFO @ 26513.192625 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got * | 1 test run | |||
| chip_sw_all_escalation_resets | 69045626267063515643615827236962437752735202322706015444005576623749262389243 | 317 |
UVM_INFO @ 3614.408120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|