Simulation Results: clkmgr

 
30/05/2026 15:09:44 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.41 %
  • code
  • 98.93 %
  • assert
  • 96.47 %
  • func
  • 87.82 %
  • line
  • 99.33 %
  • branch
  • 99.16 %
  • cond
  • 96.14 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
84.14%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
clkmgr_smoke 1.500s 89.526us 10 10 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.230s 31.854us 1 1 100.00
csr_rw 5 5 100.00
clkmgr_csr_rw 1.230s 17.386us 5 5 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 3.950s 209.156us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.750s 43.960us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.850s 48.476us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
clkmgr_csr_rw 1.230s 17.386us 5 5 100.00
clkmgr_csr_aliasing 1.750s 43.960us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 10 10 100.00
clkmgr_peri 1.310s 79.387us 10 10 100.00
trans_enables 10 10 100.00
clkmgr_trans 1.920s 166.024us 10 10 100.00
extclk 10 10 100.00
clkmgr_extclk 1.440s 95.670us 10 10 100.00
clk_status 10 10 100.00
clkmgr_clk_status 1.400s 200.573us 10 10 100.00
jitter 10 10 100.00
clkmgr_smoke 1.500s 89.526us 10 10 100.00
frequency 10 10 100.00
clkmgr_frequency 16.850s 2240.583us 10 10 100.00
frequency_timeout 10 10 100.00
clkmgr_frequency_timeout 12.610s 2421.219us 10 10 100.00
frequency_overflow 10 10 100.00
clkmgr_frequency 16.850s 2240.583us 10 10 100.00
stress_all 10 10 100.00
clkmgr_stress_all 47.320s 9997.520us 10 10 100.00
alert_test 10 10 100.00
clkmgr_alert_test 1.290s 61.280us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
clkmgr_tl_errors 5.140s 492.948us 25 25 100.00
tl_d_illegal_access 25 25 100.00
clkmgr_tl_errors 5.140s 492.948us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
clkmgr_csr_hw_reset 1.230s 31.854us 1 1 100.00
clkmgr_csr_rw 1.230s 17.386us 5 5 100.00
clkmgr_csr_aliasing 1.750s 43.960us 1 1 100.00
clkmgr_same_csr_outstanding 2.140s 198.107us 5 5 100.00
tl_d_partial_access 12 12 100.00
clkmgr_csr_hw_reset 1.230s 31.854us 1 1 100.00
clkmgr_csr_rw 1.230s 17.386us 5 5 100.00
clkmgr_csr_aliasing 1.750s 43.960us 1 1 100.00
clkmgr_same_csr_outstanding 2.140s 198.107us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 21 30 70.00
clkmgr_sec_cm 43.790s 10296.628us 3 5 60.00
clkmgr_tl_intg_err 60.570s 10051.983us 18 25 72.00
shadow_reg_update_error 11 20 55.00
clkmgr_shadow_reg_errors 1269.210s 200000.000us 11 20 55.00
shadow_reg_read_clear_staged_value 11 20 55.00
clkmgr_shadow_reg_errors 1269.210s 200000.000us 11 20 55.00
shadow_reg_storage_error 11 20 55.00
clkmgr_shadow_reg_errors 1269.210s 200000.000us 11 20 55.00
shadowed_reset_glitch 11 20 55.00
clkmgr_shadow_reg_errors 1269.210s 200000.000us 11 20 55.00
shadow_reg_update_error_with_csr_rw 15 20 75.00
clkmgr_shadow_reg_errors_with_csr_rw 994.220s 200000.000us 15 20 75.00
sec_cm_bus_integrity 18 25 72.00
clkmgr_tl_intg_err 60.570s 10051.983us 18 25 72.00
sec_cm_meas_clk_bkgn_chk 10 10 100.00
clkmgr_frequency 16.850s 2240.583us 10 10 100.00
sec_cm_timeout_clk_bkgn_chk 10 10 100.00
clkmgr_frequency_timeout 12.610s 2421.219us 10 10 100.00
sec_cm_meas_config_shadow 11 20 55.00
clkmgr_shadow_reg_errors 1269.210s 200000.000us 11 20 55.00
sec_cm_idle_intersig_mubi 10 10 100.00
clkmgr_idle_intersig_mubi 2.510s 359.253us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
clkmgr_lc_ctrl_intersig_mubi 1.420s 39.525us 10 10 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 10 10 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.430s 217.265us 10 10 100.00
sec_cm_clk_handshake_intersig_mubi 10 10 100.00
clkmgr_clk_handshake_intersig_mubi 1.730s 167.330us 10 10 100.00
sec_cm_div_intersig_mubi 10 10 100.00
clkmgr_div_intersig_mubi 1.760s 172.385us 10 10 100.00
sec_cm_jitter_config_mubi 5 5 100.00
clkmgr_csr_rw 1.230s 17.386us 5 5 100.00
sec_cm_idle_ctr_redun 3 5 60.00
clkmgr_sec_cm 43.790s 10296.628us 3 5 60.00
sec_cm_meas_config_regwen 5 5 100.00
clkmgr_csr_rw 1.230s 17.386us 5 5 100.00
sec_cm_clk_ctrl_config_regwen 5 5 100.00
clkmgr_csr_rw 1.230s 17.386us 5 5 100.00
prim_count_check 3 5 60.00
clkmgr_sec_cm 43.790s 10296.628us 3 5 60.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 10 10 100.00
clkmgr_regwen 7.890s 1202.551us 10 10 100.00
stress_all_with_rand_reset 10 10 100.00
clkmgr_stress_all_with_rand_reset 125.670s 41959.783us 10 10 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 11 test runs
clkmgr_shadow_reg_errors 46479892228763327359165410425542452517754620606886075072561502083617524887204 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 28983822524012802061065713364148166827285975510946933826994494047961209372221 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 38135570811376130314041607195647900192913335063091959306392375093997599249285 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 112627597478036786208674583043154052636973519375894172675548555295213144370891 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 22487899368385485957531503032081381713445948669592174661085683474872563904961 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 104611291586710891487146082155120834670251015174388108361526991365211160098217 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 36296073487871119268532319813856228301684504625866211458126153017821986321084 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 31771520045564507466814593635783128417664148189559120043699418476326763315677 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 41072453090251925279024407720626810394830663482792066042780868145742704557738 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 78240941007093706532507096285626403304302500217904233614331228309230089716230 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 61006856193771967696620011729646789346803182122763722957382506614055891295506 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 8 test runs
clkmgr_tl_intg_err 68384822558269432928740618622525383453739122754438746965668216155844353727497 125
UVM_INFO @ 10051982567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 57055237232472888156772097063691133526672734089416378993017545254681697161231 158
UVM_INFO @ 10296627984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 97236527564206915085857878059690826178665335476841672376804764934950172746891 134
UVM_INFO @ 10047255718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 57281321363734642154152114939705513064212982391594327479693283193123293422037 116
UVM_INFO @ 10029503127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 2641928330928374289590373572564187250039985390647273129925471423955968046843 127
UVM_INFO @ 10032211126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 1159399343812498166040348864127353584938548602010772198332110750230902569225 105
UVM_INFO @ 10034668229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 8666846603453210764210679561618049237028842940780686881978800156283441646603 219
UVM_INFO @ 10173796123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 64038538294696488696004092914884642389914343319318962001253567466821351340726 89
UVM_INFO @ 10021093655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 79861042504680324745228079161653584137183794674861224497693209171439143800709 209
UVM_INFO @ 305411131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.clk_hints (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 27379521881159409792813176358065606908200293210961923331101605320172067160499 75
UVM_INFO @ 2049348675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.clk_enables (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 50896740510014038421802631210312853093382949461001373589517745947923841853820 75
UVM_INFO @ 2192405494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.extclk_ctrl_regwen (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 1065055847190651724874294402979909322531771368776068875907669528057810136094 76
UVM_INFO @ 2345286812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---