Simulation Results

Simulation Results: csrng

30/05/2026 15:09:44 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.62 %

code
96.17 %

assert
96.94 %

func
90.74 %

block
98.49 %

line
99.50 %

branch
96.30 %

toggle
93.64 %

FSM
95.24 %

Validation stages

V1		100.00%
V2		98.16%
V2S		99.07%
V3		10.00%

38/38 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				25	25	100.00
	csrng_smoke	28.000s	98.640us	25	25	100.00
csr_hw_reset				1	1	100.00
	csrng_csr_hw_reset	34.000s	26.409us	1	1	100.00
csr_rw				5	5	100.00
	csrng_csr_rw	34.000s	28.313us	5	5	100.00
csr_bit_bash				1	1	100.00
	csrng_csr_bit_bash	36.000s	63.178us	1	1	100.00
csr_aliasing				1	1	100.00
	csrng_csr_aliasing	37.000s	94.196us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	csrng_csr_mem_rw_with_rand_reset	35.000s	60.179us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	csrng_csr_rw	34.000s	28.313us	5	5	100.00
	csrng_csr_aliasing	37.000s	94.196us	1	1	100.00

1283/1307 passed

98.16 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
interrupts				200	200	100.00
	csrng_intr	37.000s	92.827us	200	200	100.00
alerts				500	500	100.00
	csrng_alert	71.000s	3540.592us	500	500	100.00
err				500	500	100.00
	csrng_err	34.000s	35.447us	500	500	100.00
cmds				2	25	8.00
	csrng_cmds	70.000s	4388.147us	2	25	8.00
life cycle				2	25	8.00
	csrng_cmds	70.000s	4388.147us	2	25	8.00
stress_all				24	25	96.00
	csrng_stress_all	960.000s	53822.575us	24	25	96.00
intr_test				10	10	100.00
	csrng_intr_test	34.000s	23.794us	10	10	100.00
alert_test				10	10	100.00
	csrng_alert_test	35.000s	73.394us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	csrng_tl_errors	36.000s	2973.470us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	csrng_tl_errors	36.000s	2973.470us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	csrng_csr_hw_reset	34.000s	26.409us	1	1	100.00
	csrng_csr_rw	34.000s	28.313us	5	5	100.00
	csrng_csr_aliasing	37.000s	94.196us	1	1	100.00
	csrng_same_csr_outstanding	35.000s	120.906us	5	5	100.00
tl_d_partial_access				12	12	100.00
	csrng_csr_hw_reset	34.000s	26.409us	1	1	100.00
	csrng_csr_rw	34.000s	28.313us	5	5	100.00
	csrng_csr_aliasing	37.000s	94.196us	1	1	100.00
	csrng_same_csr_outstanding	35.000s	120.906us	5	5	100.00

V2S

1273/1285 passed

99.07 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	csrng_sec_cm	31.000s	181.805us	5	5	100.00
	csrng_tl_intg_err	10.000s	296.730us	25	25	100.00
sec_cm_config_regwen				19	30	63.33
	csrng_regwen	33.000s	10.203us	14	25	56.00
	csrng_csr_rw	34.000s	28.313us	5	5	100.00
sec_cm_config_mubi				500	500	100.00
	csrng_alert	71.000s	3540.592us	500	500	100.00
sec_cm_intersig_mubi				24	25	96.00
	csrng_stress_all	960.000s	53822.575us	24	25	96.00
sec_cm_main_sm_fsm_sparse				705	705	100.00
	csrng_intr	37.000s	92.827us	200	200	100.00
	csrng_err	34.000s	35.447us	500	500	100.00
	csrng_sec_cm	31.000s	181.805us	5	5	100.00
sec_cm_cmd_stage_fsm_sparse				705	705	100.00
	csrng_intr	37.000s	92.827us	200	200	100.00
	csrng_err	34.000s	35.447us	500	500	100.00
	csrng_sec_cm	31.000s	181.805us	5	5	100.00
sec_cm_ctr_drbg_fsm_sparse				705	705	100.00
	csrng_intr	37.000s	92.827us	200	200	100.00
	csrng_err	34.000s	35.447us	500	500	100.00
	csrng_sec_cm	31.000s	181.805us	5	5	100.00
sec_cm_ctr_drbg_ctr_redun				705	705	100.00
	csrng_intr	37.000s	92.827us	200	200	100.00
	csrng_err	34.000s	35.447us	500	500	100.00
	csrng_sec_cm	31.000s	181.805us	5	5	100.00
sec_cm_gen_cmd_ctr_redun				705	705	100.00
	csrng_intr	37.000s	92.827us	200	200	100.00
	csrng_err	34.000s	35.447us	500	500	100.00
	csrng_sec_cm	31.000s	181.805us	5	5	100.00
sec_cm_ctrl_mubi				500	500	100.00
	csrng_alert	71.000s	3540.592us	500	500	100.00
sec_cm_main_sm_ctr_local_esc				700	700	100.00
	csrng_intr	37.000s	92.827us	200	200	100.00
	csrng_err	34.000s	35.447us	500	500	100.00
sec_cm_constants_lc_gated				24	25	96.00
	csrng_stress_all	960.000s	53822.575us	24	25	96.00
sec_cm_sw_genbits_bus_consistency				500	500	100.00
	csrng_alert	71.000s	3540.592us	500	500	100.00
sec_cm_tile_link_bus_integrity				25	25	100.00
	csrng_tl_intg_err	10.000s	296.730us	25	25	100.00
sec_cm_aes_cipher_fsm_sparse				705	705	100.00
	csrng_intr	37.000s	92.827us	200	200	100.00
	csrng_err	34.000s	35.447us	500	500	100.00
	csrng_sec_cm	31.000s	181.805us	5	5	100.00
sec_cm_aes_cipher_fsm_redun				700	700	100.00
	csrng_intr	37.000s	92.827us	200	200	100.00
	csrng_err	34.000s	35.447us	500	500	100.00
sec_cm_aes_cipher_ctrl_sparse				700	700	100.00
	csrng_intr	37.000s	92.827us	200	200	100.00
	csrng_err	34.000s	35.447us	500	500	100.00
sec_cm_aes_cipher_fsm_local_esc				700	700	100.00
	csrng_intr	37.000s	92.827us	200	200	100.00
	csrng_err	34.000s	35.447us	500	500	100.00
sec_cm_aes_cipher_ctr_redun				705	705	100.00
	csrng_intr	37.000s	92.827us	200	200	100.00
	csrng_err	34.000s	35.447us	500	500	100.00
	csrng_sec_cm	31.000s	181.805us	5	5	100.00
sec_cm_aes_cipher_data_reg_local_esc				700	700	100.00
	csrng_intr	37.000s	92.827us	200	200	100.00
	csrng_err	34.000s	35.447us	500	500	100.00

1/10 passed

10.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	10	10.00
	csrng_stress_all_with_rand_reset	3601.000s	0.000us	1	10	10.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [] vs [*])				21 test runs
	csrng_cmds	23007170915008508094602776323782097329943678713066607909501985703772506181887	100	UVM_INFO @ 110128366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	76028704061260043058010614918847111595448095435270515305680225591236700924399	120	UVM_INFO @ 244450321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	69747224932258493430330543224725393218133941680785275006705716177388895560062	100	UVM_INFO @ 87889719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	8726364218822863656650609661320319149436471458262880361394922944928414087330	100	UVM_INFO @ 49463300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	38606647177998897762759875964016580400920517256186741482814562124587872265465	100	UVM_INFO @ 76728122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	68124071643680253858684373646735062746040856148286038690041366941665343296950	109	UVM_INFO @ 147080413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	115313600958305111125878828279149437133702557473072864077542167534129319537141	100	UVM_INFO @ 395054711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	105116289166519529763760184427854897630289784472483993340782184103108726077283	100	UVM_INFO @ 50854637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	109239235919636887442894745703365049415988249035898375353075667531998532888209	100	UVM_INFO @ 6179914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	107793160624361966288738173087126580782669318859181589579678055944942230035525	100	UVM_INFO @ 142496011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	24111608849363705798474263267577432548484114270102411294565416997163133830865	110	UVM_INFO @ 713862915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	20386883344826299001275158370365442350019465149624236770525125425354312213828	100	UVM_INFO @ 53420374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	29641758133783578275668462440478088424944676493445305419511069959502292849103	100	UVM_INFO @ 41689213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	105612275242004508801164947567230675071128935259819498483387730009620597740612	100	UVM_INFO @ 64880764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	50828121617835613569321062038077179472062370662013431129678700462709440485776	100	UVM_INFO @ 319899068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	92535106130377345698381133821714359221867671903818689334642072139892298397483	100	UVM_INFO @ 76918049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	33714718161390551015398142704024472545157498596208509019726631964204690149297	100	UVM_INFO @ 121565843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	91575520282606116167012417526080669103045008246141065875871130580143848673036	100	UVM_INFO @ 167676509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	41317066822793982615006401834239998284189346905437697708178139376497330565739	100	UVM_INFO @ 201756265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	70650129242852412662308474012815139158844943782861632532613698918365238989646	100	UVM_INFO @ 62857983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	52431194720360547958454402959114259342056688578150724818121829745348265455830	100	UVM_INFO @ 81753376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE				8 test runs
	csrng_regwen	87511530834564659250992632188612440234643464318827632692948717000850301237456	99	UVM_INFO @ 5400808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	36921320300789910397767501397424287859787522410321514271536274461730819284103	99	UVM_INFO @ 2693372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	28788136634722783636522142082873436664818056982157570429429995005343262727535	99	UVM_INFO @ 5620492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	98803920134212091509085746149894754321923885917154882427119092951252285720595	99	UVM_INFO @ 1173922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	258125707062625928943702228841971394995619090743754144349596805750971115934	99	UVM_INFO @ 7175352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	85624626051665649949038613429312165897931888630108789742667934297123651320889	99	UVM_INFO @ 2293427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	36737861220664441630827619310788873600296769719204637235798614348028849861991	99	UVM_INFO @ 4737815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	59476598512260063664118435031790044789530801200774805488702861107562764863738	99	UVM_INFO @ 3893821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				7 test runs
	csrng_stress_all_with_rand_reset	86185823944525820080662623817191057560855370205972439490161366997214516476645	None
	csrng_stress_all_with_rand_reset	113144462053366888608143472444305698396551702532469732861853358943261645211760	None
	csrng_stress_all_with_rand_reset	59434731922231137109332987626765090918752902605432572069070218309875061984117	None
	csrng_stress_all_with_rand_reset	68155873052306474611061364049096216095849992400127558401293854693153020716928	None
	csrng_stress_all_with_rand_reset	80150570413232768325201059913657960827351240365880024632182993877833860488826	None
	csrng_stress_all_with_rand_reset	46308185250625396287642220406681095184102431824135357426189265941750674454800	None
	csrng_stress_all_with_rand_reset	112785780923519564245268528949360898472225683538684193442848818613868298578305	None
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE				3 test runs
	csrng_regwen	114023912762236165274645276901821306179216276357885765601874739092929630487672	99	UVM_INFO @ 10203441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	24991429558687479964025196557232751399605222273305819132953451649073521932467	99	UVM_INFO @ 26004809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	85766338417280540984752309370168455770101995856370161361834522848509836396735	99	UVM_INFO @ 12213033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started				1 test run
	csrng_stress_all_with_rand_reset	19884485285223572458687831707222165437437724084684178655467389000159447928638	142	UVM_INFO @ 5229776932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_env_cfg.sv:358) [cfg] Check failed hw_v == * (* [] vs [*])				1 test run
	csrng_stress_all_with_rand_reset	100747842497248433236831467550286148973925699084882343960393098379661402809493	168	UVM_INFO @ 1945233389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:429) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: csrng_reg_block.genbits				1 test run
	csrng_cmds	92206849670225052326991135121220071480579010897682400785458054926946880060270	103	UVM_INFO @ 80538548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_scoreboard.sv:640) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [] vs [*])				1 test run
	csrng_cmds	42333071898992419617339843946005701622762641862913784594489638504831410332220	109	UVM_INFO @ 1047727756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [] vs [*]) Interrupt_pin: EntropyReq				1 test run
	csrng_stress_all	23861871385114576818713171622171630563533243941901800024813170411219819320863	116	UVM_INFO @ 4267118947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---