Simulation Results: edn/edn0

 
30/05/2026 15:09:44 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.79 %
  • code
  • 95.58 %
  • assert
  • 98.92 %
  • func
  • 92.86 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 93.96 %
  • toggle
  • 97.12 %
  • FSM
  • 91.40 %
Validation stages
V1
100.00%
V2
99.18%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.220s 76.357us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 16.620us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.020s 52.386us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.900s 107.043us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.470s 89.351us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.630s 220.127us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.020s 52.386us 5 5 100.00
edn_csr_aliasing 1.470s 89.351us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 4.570s 635.813us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 4.570s 635.813us 100 100 100.00
genbits 100 100 100.00
edn_genbits 4.570s 635.813us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.350s 28.794us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.630s 320.626us 200 200 100.00
errs 100 100 100.00
edn_err 1.550s 29.763us 100 100 100.00
disable 95 100 95.00
edn_disable 1.320s 12.755us 50 50 100.00
edn_disable_auto_req_mode 12.160s 500.000us 45 50 90.00
stress_all 30 30 100.00
edn_stress_all 8.130s 381.079us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.220s 29.949us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.180s 15.074us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 3.320s 287.195us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 3.320s 287.195us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.000s 16.620us 1 1 100.00
edn_csr_rw 1.020s 52.386us 5 5 100.00
edn_csr_aliasing 1.470s 89.351us 1 1 100.00
edn_same_csr_outstanding 1.700s 38.008us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.000s 16.620us 1 1 100.00
edn_csr_rw 1.020s 52.386us 5 5 100.00
edn_csr_aliasing 1.470s 89.351us 1 1 100.00
edn_same_csr_outstanding 1.700s 38.008us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 7.240s 2657.058us 5 5 100.00
edn_tl_intg_err 11.870s 3656.621us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.150s 15.983us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.630s 320.626us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.240s 2657.058us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.240s 2657.058us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 7.240s 2657.058us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 7.240s 2657.058us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.630s 320.626us 200 200 100.00
edn_sec_cm 7.240s 2657.058us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.630s 320.626us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 11.870s 3656.621us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 27 30 90.00
edn_stress_all_with_rand_reset 112.940s 19523.698us 27 30 90.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 3 test runs
edn_disable_auto_req_mode 39377560609932309375895978982541650542768775638472123061702608526105889291840 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 62425651605755298083171005093803144717666215569608437642522313896379118727157 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 70015524077233340740646584411300816872418110191943759421875957229471610240286 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 2 test runs
edn_disable_auto_req_mode 73505288379787747004141186320659266625720388578647653396610855041620301493559 88
UVM_INFO @ 25873464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 77348460192907538679330903187307337862402335596134501141869677831603342321665 88
UVM_INFO @ 16218861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
edn_stress_all_with_rand_reset 36922087774171617227076538189107832461562223350021471265348453817040385634913 187
UVM_INFO @ 1164650430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 12766608000849988595123606098620338583570809453559753515637725913475101393660 122
UVM_INFO @ 113651741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[FCIBH] Illegal bin hit 1 test run
edn_stress_all_with_rand_reset 101447337760752608780608443857791595466775998416549787888501183355561271207615 218
/nightly/current_run/scratch/master/edn_edn0-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25
csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 840052962 ps, Illegal
state bin il of coverpoint csrng_cmd_cp in covergroup