Simulation Results: edn/edn1

 
30/05/2026 15:09:44 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.75 %
  • code
  • 96.15 %
  • assert
  • 98.44 %
  • func
  • 92.65 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 95.00 %
  • toggle
  • 96.08 %
  • FSM
  • 96.59 %
Validation stages
V1
100.00%
V2
99.01%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.100s 20.927us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.890s 15.937us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.000s 18.634us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.690s 909.771us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.120s 124.858us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.650s 85.518us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.000s 18.634us 5 5 100.00
edn_csr_aliasing 1.120s 124.858us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 2.990s 299.040us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 2.990s 299.040us 100 100 100.00
genbits 100 100 100.00
edn_genbits 2.990s 299.040us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.290s 26.709us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.550s 30.416us 200 200 100.00
errs 100 100 100.00
edn_err 1.540s 28.927us 100 100 100.00
disable 94 100 94.00
edn_disable 1.110s 12.889us 50 50 100.00
edn_disable_auto_req_mode 7.080s 500.000us 44 50 88.00
stress_all 30 30 100.00
edn_stress_all 6.310s 334.661us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.080s 14.538us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.680s 105.290us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 3.490s 2620.641us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 3.490s 2620.641us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 0.890s 15.937us 1 1 100.00
edn_csr_rw 1.000s 18.634us 5 5 100.00
edn_csr_aliasing 1.120s 124.858us 1 1 100.00
edn_same_csr_outstanding 1.380s 509.830us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 0.890s 15.937us 1 1 100.00
edn_csr_rw 1.000s 18.634us 5 5 100.00
edn_csr_aliasing 1.120s 124.858us 1 1 100.00
edn_same_csr_outstanding 1.380s 509.830us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 3.990s 2629.328us 5 5 100.00
edn_tl_intg_err 2.790s 188.451us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.190s 17.812us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.550s 30.416us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 3.990s 2629.328us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 3.990s 2629.328us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 3.990s 2629.328us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 3.990s 2629.328us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.550s 30.416us 200 200 100.00
edn_sec_cm 3.990s 2629.328us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.550s 30.416us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 2.790s 188.451us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 27 30 90.00
edn_stress_all_with_rand_reset 97.010s 24876.809us 27 30 90.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 5 test runs
edn_disable_auto_req_mode 82149398770277309580475902995464618153028588891361814921026441025014091964044 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 33242316544173241798398994696361540917608246852637339770254844549530995478250 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 84228431708050830133380458395376617652416642120968549644778622447002249838070 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 61275285594276308885603587830181651263285925902244399119475020874444628363324 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 7227624319215381634097293659949593851999102332690155596952494422937197743800 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
edn_stress_all_with_rand_reset 22353049772521792177842185134750578167915986184803358552857670262591865701763 200
UVM_INFO @ 1501701787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 103355908929989206621357912930009169262728085804827100832647735961401522169562 199
UVM_INFO @ 1763207535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 98935381644328285632532996530786479869947293116415844514669778007933324666139 165
UVM_INFO @ 435620691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 1 test run
edn_disable_auto_req_mode 98777581897467709122431643723020834458370543840313412773615822432051301894965 88
UVM_INFO @ 23796828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---