Simulation Results: flash_ctrl

 
30/05/2026 15:09:44 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.07 %
  • code
  • 95.89 %
  • assert
  • 96.93 %
  • func
  • 98.39 %
  • line
  • 96.09 %
  • branch
  • 97.40 %
  • cond
  • 94.80 %
  • toggle
  • 98.66 %
  • FSM
  • 92.52 %
Validation stages
V1
100.00%
V2
98.82%
V2S
99.16%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
flash_ctrl_smoke 156.960s 96.459us 50 50 100.00
smoke_hw 5 5 100.00
flash_ctrl_smoke_hw 25.530s 58.077us 5 5 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 26.690s 54.743us 1 1 100.00
csr_rw 5 5 100.00
flash_ctrl_csr_rw 19.130s 80.562us 5 5 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 81.530s 3361.824us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 25.480s 430.439us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 18.030s 363.080us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
flash_ctrl_csr_rw 19.130s 80.562us 5 5 100.00
flash_ctrl_csr_aliasing 25.480s 430.439us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 6.410s 42.404us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 12.440s 20.121us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 5 5 100.00
flash_ctrl_sw_op 21.020s 409.340us 5 5 100.00
host_read_direct 5 5 100.00
flash_ctrl_host_dir_rd 68.090s 249.262us 5 5 100.00
rma_hw_if 43 43 100.00
flash_ctrl_hw_rma 1982.010s 879271.384us 3 3 100.00
flash_ctrl_hw_rma_reset 977.470s 760522.624us 20 20 100.00
flash_ctrl_lcmgr_intg 14.960s 38.950us 20 20 100.00
host_controller_arb 5 5 100.00
flash_ctrl_host_ctrl_arb 2190.160s 254168.318us 5 5 100.00
erase_suspend 5 5 100.00
flash_ctrl_erase_suspend 398.600s 13409.872us 5 5 100.00
program_reset 29 30 96.67
flash_ctrl_prog_reset 3604.012s 0.000us 29 30 96.67
full_memory_access 5 5 100.00
flash_ctrl_full_mem_access 3633.850s 99784.705us 5 5 100.00
rd_buff_eviction 5 5 100.00
flash_ctrl_rd_buff_evict 97.380s 720.234us 5 5 100.00
rd_buff_eviction_w_ecc 103 105 98.10
flash_ctrl_rw_evict 35.090s 29.486us 39 40 97.50
flash_ctrl_rw_evict_all_en 33.270s 87.166us 39 40 97.50
flash_ctrl_re_evict 38.320s 245.437us 25 25 100.00
host_arb 20 20 100.00
flash_ctrl_phy_arb 301.100s 22637.299us 20 20 100.00
host_interleave 20 20 100.00
flash_ctrl_phy_arb 301.100s 22637.299us 20 20 100.00
memory_protection 20 20 100.00
flash_ctrl_mp_regions 1001.120s 65108.983us 20 20 100.00
fetch_code 10 10 100.00
flash_ctrl_fetch_code 29.710s 2535.796us 10 10 100.00
all_partitions 20 20 100.00
flash_ctrl_rand_ops 632.860s 498.808us 20 20 100.00
error_mp 10 10 100.00
flash_ctrl_error_mp 688.770s 7376.996us 10 10 100.00
error_prog_win 10 10 100.00
flash_ctrl_error_prog_win 539.760s 443.197us 10 10 100.00
error_prog_type 5 5 100.00
flash_ctrl_error_prog_type 1479.700s 2234.507us 5 5 100.00
error_read_seed 20 20 100.00
flash_ctrl_hw_read_seed_err 15.400s 42.580us 20 20 100.00
read_write_overflow 5 5 100.00
flash_ctrl_oversize_error 142.640s 3141.046us 5 5 100.00
flash_ctrl_disable 50 50 100.00
flash_ctrl_disable 23.210s 60.113us 50 50 100.00
flash_ctrl_connect 80 80 100.00
flash_ctrl_connect 18.590s 55.964us 80 80 100.00
stress_all 5 5 100.00
flash_ctrl_stress_all 867.220s 2268.854us 5 5 100.00
secret_partition 129 130 99.23
flash_ctrl_hw_sec_otp 261.880s 51479.114us 50 50 100.00
flash_ctrl_otp_reset 138.610s 138.904us 79 80 98.75
isolation_partition 3 3 100.00
flash_ctrl_hw_rma 1982.010s 879271.384us 3 3 100.00
interrupts 95 100 95.00
flash_ctrl_intr_rd 172.190s 10184.988us 37 40 92.50
flash_ctrl_intr_wr 3604.013s 0.000us 9 10 90.00
flash_ctrl_intr_rd_slow_flash 345.330s 24411.162us 40 40 100.00
flash_ctrl_intr_wr_slow_flash 3604.012s 0.000us 9 10 90.00
invalid_op 20 20 100.00
flash_ctrl_invalid_op 74.760s 32824.712us 20 20 100.00
mid_op_rst 5 5 100.00
flash_ctrl_mid_op_rst 63.860s 4728.168us 5 5 100.00
double_bit_err 34 35 97.14
flash_ctrl_read_word_sweep_derr 22.530s 48.856us 5 5 100.00
flash_ctrl_ro_derr 125.990s 3408.539us 10 10 100.00
flash_ctrl_rw_derr 214.760s 2309.626us 10 10 100.00
flash_ctrl_derr_detect 156.200s 9907.077us 5 5 100.00
flash_ctrl_integrity 3603.134s 0.000us 4 5 80.00
single_bit_err 25 25 100.00
flash_ctrl_read_word_sweep_serr 19.650s 25.748us 5 5 100.00
flash_ctrl_ro_serr 113.140s 819.568us 10 10 100.00
flash_ctrl_rw_serr 202.330s 3649.657us 10 10 100.00
singlebit_err_counter 5 5 100.00
flash_ctrl_serr_counter 76.390s 859.836us 5 5 100.00
singlebit_err_address 5 5 100.00
flash_ctrl_serr_address 83.820s 4812.343us 5 5 100.00
scramble 61 62 98.39
flash_ctrl_wo 232.590s 12302.429us 20 20 100.00
flash_ctrl_write_word_sweep 14.220s 306.091us 1 1 100.00
flash_ctrl_read_word_sweep 14.600s 34.518us 1 1 100.00
flash_ctrl_ro 100.700s 3247.655us 20 20 100.00
flash_ctrl_rw 483.520s 6117.041us 19 20 95.00
filesystem_support 5 5 100.00
flash_ctrl_fs_sup 36.270s 665.719us 5 5 100.00
rma_write_process_error 23 23 100.00
flash_ctrl_rma_err 924.530s 163794.144us 3 3 100.00
flash_ctrl_hw_prog_rma_wipe_err 258.440s 10020.190us 20 20 100.00
alert_test 10 10 100.00
flash_ctrl_alert_test 14.130s 34.437us 10 10 100.00
intr_test 10 10 100.00
flash_ctrl_intr_test 15.340s 31.688us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
flash_ctrl_tl_errors 20.670s 101.394us 25 25 100.00
tl_d_illegal_access 25 25 100.00
flash_ctrl_tl_errors 20.670s 101.394us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
flash_ctrl_csr_hw_reset 26.690s 54.743us 1 1 100.00
flash_ctrl_csr_rw 19.130s 80.562us 5 5 100.00
flash_ctrl_csr_aliasing 25.480s 430.439us 1 1 100.00
flash_ctrl_same_csr_outstanding 27.180s 117.654us 5 5 100.00
tl_d_partial_access 12 12 100.00
flash_ctrl_csr_hw_reset 26.690s 54.743us 1 1 100.00
flash_ctrl_csr_rw 19.130s 80.562us 5 5 100.00
flash_ctrl_csr_aliasing 25.480s 430.439us 1 1 100.00
flash_ctrl_same_csr_outstanding 27.180s 117.654us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
flash_ctrl_shadow_reg_errors 65.810s 181.429us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
flash_ctrl_shadow_reg_errors 65.810s 181.429us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
flash_ctrl_shadow_reg_errors 65.810s 181.429us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
flash_ctrl_shadow_reg_errors 65.810s 181.429us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 84.850s 408.697us 20 20 100.00
tl_intg_err 29 30 96.67
flash_ctrl_sec_cm 2372.520s 2108.846us 4 5 80.00
flash_ctrl_tl_intg_err 601.360s 655.986us 25 25 100.00
sec_cm_reg_bus_integrity 25 25 100.00
flash_ctrl_tl_intg_err 601.360s 655.986us 25 25 100.00
sec_cm_host_bus_integrity 25 25 100.00
flash_ctrl_tl_intg_err 601.360s 655.986us 25 25 100.00
sec_cm_mem_bus_integrity 6 6 100.00
flash_ctrl_rd_intg 32.590s 626.856us 3 3 100.00
flash_ctrl_wr_intg 13.780s 125.246us 3 3 100.00
sec_cm_scramble_key_sideload 50 50 100.00
flash_ctrl_smoke 156.960s 96.459us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 259 260 99.62
flash_ctrl_otp_reset 138.610s 138.904us 79 80 98.75
flash_ctrl_disable 23.210s 60.113us 50 50 100.00
flash_ctrl_sec_info_access 83.490s 12773.221us 50 50 100.00
flash_ctrl_connect 18.590s 55.964us 80 80 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
flash_ctrl_config_regwen 12.590s 123.466us 5 5 100.00
sec_cm_data_regions_config_regwen 5 5 100.00
flash_ctrl_csr_rw 19.130s 80.562us 5 5 100.00
sec_cm_data_regions_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 65.810s 181.429us 20 20 100.00
sec_cm_info_regions_config_regwen 5 5 100.00
flash_ctrl_csr_rw 19.130s 80.562us 5 5 100.00
sec_cm_info_regions_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 65.810s 181.429us 20 20 100.00
sec_cm_bank_config_regwen 5 5 100.00
flash_ctrl_csr_rw 19.130s 80.562us 5 5 100.00
sec_cm_bank_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 65.810s 181.429us 20 20 100.00
sec_cm_mem_ctrl_global_esc 50 50 100.00
flash_ctrl_disable 23.210s 60.113us 50 50 100.00
sec_cm_mem_ctrl_local_esc 6 6 100.00
flash_ctrl_rd_intg 32.590s 626.856us 3 3 100.00
flash_ctrl_access_after_disable 12.860s 20.549us 3 3 100.00
sec_cm_mem_addr_infection 3 3 100.00
flash_ctrl_host_addr_infection 25.620s 63.218us 3 3 100.00
sec_cm_mem_disable_config_mubi 50 50 100.00
flash_ctrl_disable 23.210s 60.113us 50 50 100.00
sec_cm_exec_config_redun 10 10 100.00
flash_ctrl_fetch_code 29.710s 2535.796us 10 10 100.00
sec_cm_mem_scramble 19 20 95.00
flash_ctrl_rw 483.520s 6117.041us 19 20 95.00
sec_cm_mem_integrity 24 25 96.00
flash_ctrl_rw_serr 202.330s 3649.657us 10 10 100.00
flash_ctrl_rw_derr 214.760s 2309.626us 10 10 100.00
flash_ctrl_integrity 3603.134s 0.000us 4 5 80.00
sec_cm_rma_entry_mem_sec_wipe 3 3 100.00
flash_ctrl_hw_rma 1982.010s 879271.384us 3 3 100.00
sec_cm_ctrl_fsm_sparse 4 5 80.00
flash_ctrl_sec_cm 2372.520s 2108.846us 4 5 80.00
sec_cm_phy_fsm_sparse 4 5 80.00
flash_ctrl_sec_cm 2372.520s 2108.846us 4 5 80.00
sec_cm_phy_prog_fsm_sparse 4 5 80.00
flash_ctrl_sec_cm 2372.520s 2108.846us 4 5 80.00
sec_cm_ctr_redun 4 5 80.00
flash_ctrl_sec_cm 2372.520s 2108.846us 4 5 80.00
sec_cm_phy_arbiter_ctrl_redun 5 5 100.00
flash_ctrl_phy_arb_redun 19.400s 914.593us 5 5 100.00
sec_cm_phy_host_grant_ctrl_consistency 5 5 100.00
flash_ctrl_phy_host_grant_err 15.130s 39.301us 5 5 100.00
sec_cm_phy_ack_ctrl_consistency 5 5 100.00
flash_ctrl_phy_ack_consistency 14.640s 71.980us 5 5 100.00
sec_cm_fifo_ctr_redun 4 5 80.00
flash_ctrl_sec_cm 2372.520s 2108.846us 4 5 80.00
sec_cm_mem_tl_lc_gate_fsm_sparse 4 5 80.00
flash_ctrl_sec_cm 2372.520s 2108.846us 4 5 80.00
sec_cm_prog_tl_lc_gate_fsm_sparse 4 5 80.00
flash_ctrl_sec_cm 2372.520s 2108.846us 4 5 80.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 24.550s 449.385us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 3 3 100.00
flash_ctrl_basic_rw 607.560s 4226.145us 3 3 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 4 test runs
flash_ctrl_integrity 29852361644677776341996033581279053964694571310687314704093536840768046855470 None
flash_ctrl_intr_wr_slow_flash 103941541381083782319037811512807304619156634593463642167937171477575711417781 None
flash_ctrl_intr_wr 22375612534554621891228663293025592283203911531118996863830269521088635772047 None
flash_ctrl_prog_reset 79407848738887898838879814920393098263673224267271212489473505265840178003368 None
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * 2 test runs
flash_ctrl_rw_evict 8514319824636698862399000451314066324027616255892905122172037306914487964736 108
UVM_INFO @ 16947.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
flash_ctrl_rw_evict_all_en 33564034407305024800397689750963726749179372811578350993476987987023273962504 108
UVM_INFO @ 21258.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [flash_ctrl_common_vseq] wait timeout occurred! 1 test run
flash_ctrl_sec_cm 65118050876044264082406245452272637097517430681561572715126228918973859492916 1355
UVM_INFO @ 10780088.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'dst_req_o' 1 test run
flash_ctrl_otp_reset 75931533344375247299459012486020357628396472626242921928869034002443687390585 124
UVM_ERROR @ 3042.6 ns: (prim_sync_reqack.sv:355) [ASSERT FAILED] SyncReqAckAckNeedsReq
UVM_INFO @ 3042.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:267) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly 1 test run
flash_ctrl_rw 82614831519367994852285058463492548176608987259761060593179495782612709208333 108
UVM_INFO @ 20814193.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] *: obs:exp *dfd1bb2_390b95d4:ffffffff_390b95d* mismatch!! 1 test run
flash_ctrl_intr_rd 15800776219943492797269725159305532238663413246050303421552322362882192563914 108
UVM_INFO @ 616707.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] *: obs:exp *da_ff76084f:ffffffff_ffffffff mismatch!! 1 test run
flash_ctrl_intr_rd 57524104836787478836793033858125339521343354458694641947061095517039764127088 108
UVM_INFO @ 1519054.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] *: obs:exp *b74d9_d833e5a7:ffffffff_d833e5a* mismatch!! 1 test run
flash_ctrl_intr_rd 74653368051360893006246215388215003030306692200692182018651341260189714069129 108
UVM_INFO @ 3983264.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---