Simulation Results: hmac

 
30/05/2026 15:09:44 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 99.47 %
  • code
  • 99.29 %
  • assert
  • 99.12 %
  • func
  • 100.00 %
  • line
  • 99.90 %
  • branch
  • 99.83 %
  • cond
  • 96.74 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 12.980s 1212.926us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.090s 21.350us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 1.170s 31.479us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.170s 115.620us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.100s 800.198us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 3.280s 109.795us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 1.170s 31.479us 5 5 100.00
hmac_csr_aliasing 6.100s 800.198us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 110.930s 12174.299us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 99.080s 2216.288us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 256.380s 29402.901us 30 30 100.00
hmac_test_sha384_vectors 595.100s 98108.820us 75 75 100.00
hmac_test_sha512_vectors 633.250s 77404.800us 75 75 100.00
hmac_test_hmac256_vectors 13.150s 1218.722us 50 50 100.00
hmac_test_hmac384_vectors 15.870s 866.046us 60 60 100.00
hmac_test_hmac512_vectors 19.280s 514.782us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 42.160s 5910.128us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1214.960s 15503.134us 10 10 100.00
error 10 10 100.00
hmac_error 88.230s 9126.498us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 107.220s 21630.303us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 12.980s 1212.926us 10 10 100.00
hmac_long_msg 110.930s 12174.299us 10 10 100.00
hmac_back_pressure 99.080s 2216.288us 25 25 100.00
hmac_datapath_stress 1214.960s 15503.134us 10 10 100.00
hmac_burst_wr 42.160s 5910.128us 50 50 100.00
hmac_stress_all 2775.160s 104401.060us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 12.980s 1212.926us 10 10 100.00
hmac_long_msg 110.930s 12174.299us 10 10 100.00
hmac_back_pressure 99.080s 2216.288us 25 25 100.00
hmac_datapath_stress 1214.960s 15503.134us 10 10 100.00
hmac_wipe_secret 107.220s 21630.303us 10 10 100.00
hmac_test_sha256_vectors 256.380s 29402.901us 30 30 100.00
hmac_test_sha384_vectors 595.100s 98108.820us 75 75 100.00
hmac_test_sha512_vectors 633.250s 77404.800us 75 75 100.00
hmac_test_hmac256_vectors 13.150s 1218.722us 50 50 100.00
hmac_test_hmac384_vectors 15.870s 866.046us 60 60 100.00
hmac_test_hmac512_vectors 19.280s 514.782us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 12.980s 1212.926us 10 10 100.00
hmac_long_msg 110.930s 12174.299us 10 10 100.00
hmac_back_pressure 99.080s 2216.288us 25 25 100.00
hmac_datapath_stress 1214.960s 15503.134us 10 10 100.00
hmac_burst_wr 42.160s 5910.128us 50 50 100.00
hmac_error 88.230s 9126.498us 10 10 100.00
hmac_wipe_secret 107.220s 21630.303us 10 10 100.00
hmac_test_sha256_vectors 256.380s 29402.901us 30 30 100.00
hmac_test_sha384_vectors 595.100s 98108.820us 75 75 100.00
hmac_test_sha512_vectors 633.250s 77404.800us 75 75 100.00
hmac_test_hmac256_vectors 13.150s 1218.722us 50 50 100.00
hmac_test_hmac384_vectors 15.870s 866.046us 60 60 100.00
hmac_test_hmac512_vectors 19.280s 514.782us 75 75 100.00
hmac_stress_all 2775.160s 104401.060us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 2775.160s 104401.060us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 0.950s 22.534us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 0.970s 11.898us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 4.730s 277.865us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 4.730s 277.865us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 1.090s 21.350us 1 1 100.00
hmac_csr_rw 1.170s 31.479us 5 5 100.00
hmac_csr_aliasing 6.100s 800.198us 1 1 100.00
hmac_same_csr_outstanding 2.440s 154.013us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 1.090s 21.350us 1 1 100.00
hmac_csr_rw 1.170s 31.479us 5 5 100.00
hmac_csr_aliasing 6.100s 800.198us 1 1 100.00
hmac_same_csr_outstanding 2.440s 154.013us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 1.250s 50.006us 5 5 100.00
hmac_tl_intg_err 5.250s 275.896us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 5.250s 275.896us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 12.980s 1212.926us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 6.260s 260.997us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 550.210s 240489.065us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.110s 11.278us 1 1 100.00