Simulation Results: keymgr

 
30/05/2026 15:09:44 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.95 %
  • code
  • 98.96 %
  • assert
  • 97.72 %
  • func
  • 91.16 %
  • line
  • 99.20 %
  • branch
  • 99.00 %
  • cond
  • 98.04 %
  • toggle
  • 98.54 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.53%
V2S
99.38%
V3
35.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 30 30 100.00
keymgr_smoke 19.640s 2942.974us 30 30 100.00
random 30 30 100.00
keymgr_random 51.480s 2554.188us 30 30 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.330s 38.371us 1 1 100.00
csr_rw 5 5 100.00
keymgr_csr_rw 1.600s 103.949us 5 5 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 35.530s 3018.784us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 6.180s 256.522us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
keymgr_csr_mem_rw_with_rand_reset 1.970s 31.023us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
keymgr_csr_rw 1.600s 103.949us 5 5 100.00
keymgr_csr_aliasing 6.180s 256.522us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 49 50 98.00
keymgr_cfg_regwen 66.260s 8559.801us 49 50 98.00
sideload 80 80 100.00
keymgr_sideload 8.680s 327.195us 20 20 100.00
keymgr_sideload_kmac 15.280s 1488.003us 20 20 100.00
keymgr_sideload_aes 37.750s 2419.214us 20 20 100.00
keymgr_sideload_otbn 29.870s 1600.255us 20 20 100.00
direct_to_disabled_state 30 30 100.00
keymgr_direct_to_disabled 16.460s 6102.460us 30 30 100.00
lc_disable 50 50 100.00
keymgr_lc_disable 19.940s 678.000us 50 50 100.00
kmac_error_response 20 20 100.00
keymgr_kmac_rsp_err 6.790s 154.703us 20 20 100.00
invalid_sw_input 20 20 100.00
keymgr_sw_invalid_input 25.730s 2290.313us 20 20 100.00
invalid_hw_input 50 50 100.00
keymgr_hwsw_invalid_input 47.760s 1751.646us 50 50 100.00
sync_async_fault_cross 20 20 100.00
keymgr_sync_async_fault_cross 6.900s 845.675us 20 20 100.00
stress_all 49 50 98.00
keymgr_stress_all 234.230s 12605.459us 49 50 98.00
intr_test 10 10 100.00
keymgr_intr_test 1.350s 82.448us 10 10 100.00
alert_test 10 10 100.00
keymgr_alert_test 1.430s 33.134us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
keymgr_tl_errors 4.240s 315.914us 25 25 100.00
tl_d_illegal_access 25 25 100.00
keymgr_tl_errors 4.240s 315.914us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
keymgr_csr_hw_reset 1.330s 38.371us 1 1 100.00
keymgr_csr_rw 1.600s 103.949us 5 5 100.00
keymgr_csr_aliasing 6.180s 256.522us 1 1 100.00
keymgr_same_csr_outstanding 2.010s 86.189us 5 5 100.00
tl_d_partial_access 12 12 100.00
keymgr_csr_hw_reset 1.330s 38.371us 1 1 100.00
keymgr_csr_rw 1.600s 103.949us 5 5 100.00
keymgr_csr_aliasing 6.180s 256.522us 1 1 100.00
keymgr_same_csr_outstanding 2.010s 86.189us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 20.460s 1080.496us 5 5 100.00
tl_intg_err 30 30 100.00
keymgr_sec_cm 20.460s 1080.496us 5 5 100.00
keymgr_tl_intg_err 9.980s 474.063us 25 25 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 7.470s 270.726us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 7.470s 270.726us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 7.470s 270.726us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 7.470s 270.726us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 16.740s 600.612us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 20.460s 1080.496us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 20.460s 1080.496us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
keymgr_tl_intg_err 9.980s 474.063us 25 25 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 7.470s 270.726us 20 20 100.00
sec_cm_op_config_regwen 49 50 98.00
keymgr_cfg_regwen 66.260s 8559.801us 49 50 98.00
sec_cm_reseed_config_regwen 35 35 100.00
keymgr_random 51.480s 2554.188us 30 30 100.00
keymgr_csr_rw 1.600s 103.949us 5 5 100.00
sec_cm_sw_binding_config_regwen 35 35 100.00
keymgr_random 51.480s 2554.188us 30 30 100.00
keymgr_csr_rw 1.600s 103.949us 5 5 100.00
sec_cm_max_key_ver_config_regwen 35 35 100.00
keymgr_random 51.480s 2554.188us 30 30 100.00
keymgr_csr_rw 1.600s 103.949us 5 5 100.00
sec_cm_lc_ctrl_intersig_mubi 50 50 100.00
keymgr_lc_disable 19.940s 678.000us 50 50 100.00
sec_cm_constants_consistency 50 50 100.00
keymgr_hwsw_invalid_input 47.760s 1751.646us 50 50 100.00
sec_cm_intersig_consistency 50 50 100.00
keymgr_hwsw_invalid_input 47.760s 1751.646us 50 50 100.00
sec_cm_hw_key_sw_noaccess 30 30 100.00
keymgr_random 51.480s 2554.188us 30 30 100.00
sec_cm_output_keys_ctrl_redun 20 20 100.00
keymgr_sideload_protect 32.000s 3284.858us 20 20 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 20.460s 1080.496us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 20.460s 1080.496us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 20.460s 1080.496us 5 5 100.00
sec_cm_ctrl_fsm_consistency 49 50 98.00
keymgr_custom_cm 39.050s 2229.170us 49 50 98.00
sec_cm_ctrl_fsm_global_esc 50 50 100.00
keymgr_lc_disable 19.940s 678.000us 50 50 100.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 20.460s 1080.496us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 20.460s 1080.496us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 20.460s 1080.496us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 49 50 98.00
keymgr_custom_cm 39.050s 2229.170us 49 50 98.00
sec_cm_kmac_if_done_ctrl_consistency 49 50 98.00
keymgr_custom_cm 39.050s 2229.170us 49 50 98.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 20.460s 1080.496us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 49 50 98.00
keymgr_custom_cm 39.050s 2229.170us 49 50 98.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 20.460s 1080.496us 5 5 100.00
sec_cm_ctrl_key_integrity 49 50 98.00
keymgr_custom_cm 39.050s 2229.170us 49 50 98.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 7 20 35.00
keymgr_stress_all_with_rand_reset 34.150s 779.955us 7 20 35.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 12 test runs
keymgr_stress_all_with_rand_reset 60195314301733660209269008022859897944203465229362648847323945789716648018176 402
UVM_INFO @ 3656983048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 18405722882144088107114263339943112736364143801685572149690339157228674949644 1610
UVM_INFO @ 1221033082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 18341043380212586143679025455007495236805348615117217487932899068158944275456 574
UVM_INFO @ 237554509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 24849073325981096992544961174697510730621087655448811414902950855599807121995 873
UVM_INFO @ 993674196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 46120118276697115745347143570617419020810738162303084178891194245888333618207 387
UVM_INFO @ 169137977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 87200441733330187938305068447337807995403912457725531110053357431447215984289 1365
UVM_INFO @ 1932033849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 21073288676763509669737988662625227152435219560116659244340452007901392433802 325
UVM_INFO @ 383529798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 49935508346039045341904454932250875347096745658609694004200703566206131742349 162
UVM_INFO @ 212972139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 17207775019220814070158848301758344060587965337050352136187798623484957914804 152
UVM_INFO @ 406764734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 16588087758665014455512539998015090804650599465517988404099882212707858022908 553
UVM_INFO @ 215079891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 85580124336837184849740049900394775050422055553783092558022937855511822077107 305
UVM_INFO @ 284618694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 9195472856756706213476584055170323869691439077012698319766089709721632301153 542
UVM_INFO @ 294252616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share0_output_* 1 test run
keymgr_stress_all 37515120601016299821330077927505605319972476304242724682839858287681454801215 138
UVM_INFO @ 97148325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.start 1 test run
keymgr_cfg_regwen 56251473836073057765213104848627893512924436063800953919665841784101896892769 87
UVM_INFO @ 3545147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1199) [keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. 1 test run
keymgr_stress_all_with_rand_reset 103615240023505373148814762841002101852170166908793750773015586859925503591767 612
UVM_INFO @ 727731731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (keymgr_if.sv:403) [keymgr_if] wait timeout occurred! 1 test run
keymgr_custom_cm 93138042795567968408202540685025978598616111060699496650522259876960293185999 197
UVM_INFO @ 10681816171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---