Simulation Results: kmac/masked

 
30/05/2026 15:09:44 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.84 %
  • code
  • 94.55 %
  • assert
  • 97.98 %
  • func
  • 97.99 %
  • line
  • 99.25 %
  • branch
  • 97.10 %
  • cond
  • 94.81 %
  • toggle
  • 99.89 %
  • FSM
  • 81.69 %
Validation stages
V1
100.00%
V2
100.00%
V2S
99.41%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
kmac_smoke 78.790s 17308.259us 20 20 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.260s 91.585us 1 1 100.00
csr_rw 5 5 100.00
kmac_csr_rw 1.460s 68.485us 5 5 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 17.380s 1726.029us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 5.540s 524.092us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
kmac_csr_mem_rw_with_rand_reset 2.590s 88.016us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
kmac_csr_rw 1.460s 68.485us 5 5 100.00
kmac_csr_aliasing 5.540s 524.092us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 1.100s 22.796us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.620s 251.973us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 20 20 100.00
kmac_long_msg_and_output 5046.790s 133942.094us 20 20 100.00
burst_write 20 20 100.00
kmac_burst_write 1392.980s 164906.644us 20 20 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2913.410s 193907.326us 5 5 100.00
kmac_test_vectors_sha3_256 2688.970s 103195.627us 5 5 100.00
kmac_test_vectors_sha3_384 2016.270s 80938.167us 5 5 100.00
kmac_test_vectors_sha3_512 1381.340s 190967.480us 5 5 100.00
kmac_test_vectors_shake_128 3236.070s 692615.038us 5 5 100.00
kmac_test_vectors_shake_256 2751.070s 175134.287us 5 5 100.00
kmac_test_vectors_kmac 2.930s 414.689us 5 5 100.00
kmac_test_vectors_kmac_xof 3.310s 311.284us 5 5 100.00
sideload 20 20 100.00
kmac_sideload 460.810s 94802.499us 20 20 100.00
app 25 25 100.00
kmac_app 375.350s 165218.502us 25 25 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 308.440s 32386.769us 10 10 100.00
entropy_refresh 20 20 100.00
kmac_entropy_refresh 403.840s 186333.266us 20 20 100.00
error 20 20 100.00
kmac_error 507.990s 131891.850us 20 20 100.00
key_error 20 20 100.00
kmac_key_error 15.990s 1841.528us 20 20 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 10.340s 1095.351us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 55.670s 7926.280us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 42.000s 1995.799us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 48.500s 6518.250us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 59.920s 1860.304us 50 50 100.00
stress_all 20 20 100.00
kmac_stress_all 3477.180s 473596.340us 20 20 100.00
intr_test 10 10 100.00
kmac_intr_test 1.260s 17.654us 10 10 100.00
alert_test 10 10 100.00
kmac_alert_test 1.350s 277.711us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
kmac_tl_errors 4.600s 171.190us 25 25 100.00
tl_d_illegal_access 25 25 100.00
kmac_tl_errors 4.600s 171.190us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
kmac_csr_hw_reset 1.260s 91.585us 1 1 100.00
kmac_csr_rw 1.460s 68.485us 5 5 100.00
kmac_csr_aliasing 5.540s 524.092us 1 1 100.00
kmac_same_csr_outstanding 3.210s 120.101us 5 5 100.00
tl_d_partial_access 12 12 100.00
kmac_csr_hw_reset 1.260s 91.585us 1 1 100.00
kmac_csr_rw 1.460s 68.485us 5 5 100.00
kmac_csr_aliasing 5.540s 524.092us 1 1 100.00
kmac_same_csr_outstanding 3.210s 120.101us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.850s 115.527us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.850s 115.527us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.850s 115.527us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.850s 115.527us 20 20 100.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
kmac_shadow_reg_errors_with_csr_rw 6.160s 447.634us 19 20 95.00
tl_intg_err 30 30 100.00
kmac_sec_cm 101.050s 20244.914us 5 5 100.00
kmac_tl_intg_err 6.240s 2914.193us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
kmac_tl_intg_err 6.240s 2914.193us 25 25 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 59.920s 1860.304us 50 50 100.00
sec_cm_sw_key_key_masking 20 20 100.00
kmac_smoke 78.790s 17308.259us 20 20 100.00
sec_cm_key_sideload 20 20 100.00
kmac_sideload 460.810s 94802.499us 20 20 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.850s 115.527us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 101.050s 20244.914us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 101.050s 20244.914us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 101.050s 20244.914us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 20 20 100.00
kmac_smoke 78.790s 17308.259us 20 20 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 59.920s 1860.304us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 101.050s 20244.914us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 363.670s 18712.753us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 20 20 100.00
kmac_smoke 78.790s 17308.259us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 10 80.00
kmac_stress_all_with_rand_reset 196.430s 4243.303us 8 10 80.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:858) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) 1 test run
kmac_stress_all_with_rand_reset 60862062631488746515298542567507250608946325422327789120615395873638385626683 340
UVM_INFO @ 4754753278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
kmac_stress_all_with_rand_reset 12237845760311324593568786263659429958051042979114740972153389046713065739691 199
UVM_INFO @ 13608224740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * 1 test run
kmac_shadow_reg_errors_with_csr_rw 17801507445269601690825242308643466882958209098603615429529403935821867176416 93
UVM_INFO @ 2275635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---