Simulation Results

Simulation Results: kmac/unmasked

30/05/2026 15:09:44 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
95.71 %

code
92.23 %

assert
98.50 %

func
96.39 %

line
97.66 %

branch
95.95 %

cond
94.81 %

toggle
100.00 %

FSM
72.73 %

Validation stages

V1		100.00%
V2		94.55%
V2S		99.41%
V3		60.00%

35/35 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				20	20	100.00
	kmac_smoke	79.660s	74236.994us	20	20	100.00
csr_hw_reset				1	1	100.00
	kmac_csr_hw_reset	1.340s	39.797us	1	1	100.00
csr_rw				5	5	100.00
	kmac_csr_rw	1.530s	55.439us	5	5	100.00
csr_bit_bash				1	1	100.00
	kmac_csr_bit_bash	12.210s	856.953us	1	1	100.00
csr_aliasing				1	1	100.00
	kmac_csr_aliasing	5.770s	487.651us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	kmac_csr_mem_rw_with_rand_reset	3.000s	370.658us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	kmac_csr_rw	1.530s	55.439us	5	5	100.00
	kmac_csr_aliasing	5.770s	487.651us	1	1	100.00
mem_walk				1	1	100.00
	kmac_mem_walk	1.090s	31.986us	1	1	100.00
mem_partial_access				1	1	100.00
	kmac_mem_partial_access	1.640s	126.966us	1	1	100.00

399/422 passed

94.55 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
long_msg_and_output				20	20	100.00
	kmac_long_msg_and_output	4255.150s	180825.804us	20	20	100.00
burst_write				20	20	100.00
	kmac_burst_write	926.040s	139616.138us	20	20	100.00
test_vectors				40	40	100.00
	kmac_test_vectors_sha3_224	1580.730s	90073.474us	5	5	100.00
	kmac_test_vectors_sha3_256	1591.430s	325732.155us	5	5	100.00
	kmac_test_vectors_sha3_384	1599.220s	191899.955us	5	5	100.00
	kmac_test_vectors_sha3_512	1139.730s	239044.372us	5	5	100.00
	kmac_test_vectors_shake_128	3015.510s	123904.000us	5	5	100.00
	kmac_test_vectors_shake_256	1544.080s	111966.519us	5	5	100.00
	kmac_test_vectors_kmac	2.710s	440.738us	5	5	100.00
	kmac_test_vectors_kmac_xof	3.150s	103.738us	5	5	100.00
sideload				20	20	100.00
	kmac_sideload	437.350s	86674.993us	20	20	100.00
app				25	25	100.00
	kmac_app	306.390s	17988.675us	25	25	100.00
app_with_partial_data				10	10	100.00
	kmac_app_with_partial_data	217.790s	16129.725us	10	10	100.00
entropy_refresh				20	20	100.00
	kmac_entropy_refresh	376.250s	123280.562us	20	20	100.00
error				20	20	100.00
	kmac_error	348.860s	80716.279us	20	20	100.00
key_error				20	20	100.00
	kmac_key_error	16.380s	25915.376us	20	20	100.00
sideload_invalid				27	50	54.00
	kmac_sideload_invalid	113.810s	10113.356us	27	50	54.00
edn_timeout_error				20	20	100.00
	kmac_edn_timeout_error	38.750s	1847.283us	20	20	100.00
entropy_mode_error				20	20	100.00
	kmac_entropy_mode_error	48.820s	12866.667us	20	20	100.00
entropy_ready_error				10	10	100.00
	kmac_entropy_ready_error	69.030s	9349.772us	10	10	100.00
lc_escalation				50	50	100.00
	kmac_lc_escalation	19.100s	3568.169us	50	50	100.00
stress_all				20	20	100.00
	kmac_stress_all	2675.200s	114401.292us	20	20	100.00
intr_test				10	10	100.00
	kmac_intr_test	1.210s	23.148us	10	10	100.00
alert_test				10	10	100.00
	kmac_alert_test	1.220s	103.706us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	kmac_tl_errors	4.420s	341.273us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	kmac_tl_errors	4.420s	341.273us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	kmac_csr_hw_reset	1.340s	39.797us	1	1	100.00
	kmac_csr_rw	1.530s	55.439us	5	5	100.00
	kmac_csr_aliasing	5.770s	487.651us	1	1	100.00
	kmac_same_csr_outstanding	3.120s	238.515us	5	5	100.00
tl_d_partial_access				12	12	100.00
	kmac_csr_hw_reset	1.340s	39.797us	1	1	100.00
	kmac_csr_rw	1.530s	55.439us	5	5	100.00
	kmac_csr_aliasing	5.770s	487.651us	1	1	100.00
	kmac_same_csr_outstanding	3.120s	238.515us	5	5	100.00

V2S

169/170 passed

99.41 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	kmac_shadow_reg_errors	3.130s	188.324us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	kmac_shadow_reg_errors	3.130s	188.324us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	kmac_shadow_reg_errors	3.130s	188.324us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	kmac_shadow_reg_errors	3.130s	188.324us	20	20	100.00
shadow_reg_update_error_with_csr_rw				19	20	95.00
	kmac_shadow_reg_errors_with_csr_rw	5.780s	290.453us	19	20	95.00
tl_intg_err				30	30	100.00
	kmac_sec_cm	76.210s	13145.615us	5	5	100.00
	kmac_tl_intg_err	5.850s	2998.734us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	kmac_tl_intg_err	5.850s	2998.734us	25	25	100.00
sec_cm_lc_escalate_en_intersig_mubi				50	50	100.00
	kmac_lc_escalation	19.100s	3568.169us	50	50	100.00
sec_cm_sw_key_key_masking				20	20	100.00
	kmac_smoke	79.660s	74236.994us	20	20	100.00
sec_cm_key_sideload				20	20	100.00
	kmac_sideload	437.350s	86674.993us	20	20	100.00
sec_cm_cfg_shadowed_config_shadow				20	20	100.00
	kmac_shadow_reg_errors	3.130s	188.324us	20	20	100.00
sec_cm_fsm_sparse				5	5	100.00
	kmac_sec_cm	76.210s	13145.615us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	kmac_sec_cm	76.210s	13145.615us	5	5	100.00
sec_cm_packer_ctr_redun				5	5	100.00
	kmac_sec_cm	76.210s	13145.615us	5	5	100.00
sec_cm_cfg_shadowed_config_regwen				20	20	100.00
	kmac_smoke	79.660s	74236.994us	20	20	100.00
sec_cm_fsm_global_esc				50	50	100.00
	kmac_lc_escalation	19.100s	3568.169us	50	50	100.00
sec_cm_fsm_local_esc				5	5	100.00
	kmac_sec_cm	76.210s	13145.615us	5	5	100.00
sec_cm_absorbed_ctrl_mubi				10	10	100.00
	kmac_mubi	334.720s	20663.580us	10	10	100.00
sec_cm_sw_cmd_ctrl_sparse				20	20	100.00
	kmac_smoke	79.660s	74236.994us	20	20	100.00

6/10 passed

60.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				6	10	60.00
	kmac_stress_all_with_rand_reset	159.330s	12028.696us	6	10	60.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=2)				6 test runs
	kmac_sideload_invalid	90770881196319261022294593067747899495575593822306383915215614708771534339372	78	UVM_INFO @ 10024801562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_sideload_invalid	34896613854844122065006225427909804996896564731246540663037788670809905171175	78	UVM_INFO @ 10020165514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_sideload_invalid	6774400992434341200582188877595648343375191124090708260021025685686277997793	78	UVM_INFO @ 10047626832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_sideload_invalid	11659025253761327659898646884856557079522031785891673920999354195932593108933	78	UVM_INFO @ 10009762937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_sideload_invalid	90782142649224077460208541483435943992514534676365271889320520314860299699388	78	UVM_INFO @ 10041322386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_sideload_invalid	17701357872885854212288426645858791479499946412267682069489522953034315950931	78	UVM_INFO @ 10037640943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				4 test runs
	kmac_stress_all_with_rand_reset	35709737535376907095413968470900014212809207931477114477205253767666364867980	96	UVM_INFO @ 1233063766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_stress_all_with_rand_reset	109289551367255361691615261056077582233815973808594428259700439963658196544497	204	UVM_INFO @ 2039401183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_stress_all_with_rand_reset	68832116914070450099653599728126684332825621294923261710776370203027574421829	165	UVM_INFO @ 13012398380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_stress_all_with_rand_reset	93351875452465351663208205791972119809241606224640491314890817619547051641563	95	UVM_INFO @ 1043444050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=5)				3 test runs
	kmac_sideload_invalid	11771289948460780632818882610998383978505102412459918112824051376207509343314	82	UVM_INFO @ 10080975566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_sideload_invalid	83824413330361664479960064887475938616471809653156130210103603301163889090490	81	UVM_INFO @ 10119330184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_sideload_invalid	76779385178268053439886618456533866988635309364559633947935734504869779667256	81	UVM_INFO @ 10212295647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=3)				2 test runs
	kmac_sideload_invalid	80205368058973575924222571452862037607490469067079671037615720057252814115524	79	UVM_INFO @ 10021215754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_sideload_invalid	104127316592119591101297797681733119051715229897910999828797912111245554121207	79	UVM_INFO @ 10023306122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=9)				2 test runs
	kmac_sideload_invalid	25914828212741697231378646268869244401975040567880365096642860229859663146938	86	UVM_INFO @ 10749778223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_sideload_invalid	21998482442056793549480672734862775856589464748354256155573197321961911330778	85	UVM_INFO @ 10058802495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=4)				2 test runs
	kmac_sideload_invalid	51181110996624201971822898076351823569257272691773056452747578345936186666711	81	UVM_INFO @ 10070183438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_sideload_invalid	74729545008581366835757055150694272856590846960376284546778435793149029877784	81	UVM_INFO @ 10041238591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=13)				2 test runs
	kmac_sideload_invalid	35624865164362567679473332445244360988985824714279748335321762553899976450893	89	UVM_INFO @ 10116306817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_sideload_invalid	87360027485782575606398818632501169821771783896039670698687112640971252410860	92	UVM_INFO @ 10207256524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=8)				2 test runs
	kmac_sideload_invalid	65865538184382696904626046970349394465873162000381273374915122340257136886622	86	UVM_INFO @ 10066154926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_sideload_invalid	29400612163032217805979083006014882100420508251395178349351668492188435510621	85	UVM_INFO @ 10269082982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=7)				1 test run
	kmac_sideload_invalid	44701883605132181319136006701254108362297372162581625779994926356628626556292	84	UVM_INFO @ 10040920453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: kmac_reg_block.prefix_.prefix_* reset value: *				1 test run
	kmac_shadow_reg_errors_with_csr_rw	84251614670324872391482854239845070602798374819828190489929854818195993839422	298	UVM_INFO @ 181423603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=15)				1 test run
	kmac_sideload_invalid	89354909064169393888057776651058962659885124146036192695044774180636293063778	95	UVM_INFO @ 10113356382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=6)				1 test run
	kmac_sideload_invalid	12361862669715415075413017457374891573924103285875014762833370839592620269282	83	UVM_INFO @ 10066505321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=, Comparison=CompareOpEq, exp_data=, call_count=10)				1 test run
	kmac_sideload_invalid	21204971353841858894574192351651711617505140132294898172431759906571116803305	87	UVM_INFO @ 11347326578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---