Simulation Results: lc_ctrl/volatile_unlock_disabled

 
30/05/2026 15:09:44 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.47 %
  • code
  • 86.19 %
  • assert
  • 94.97 %
  • func
  • 96.26 %
  • line
  • 97.28 %
  • branch
  • 94.00 %
  • cond
  • 81.91 %
  • toggle
  • 89.54 %
  • FSM
  • 68.22 %
Validation stages
V1
100.00%
V2
99.30%
V2S
100.00%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 6.030s 90.777us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.520s 18.958us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.540s 20.517us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.500s 139.019us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.610s 53.045us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.980s 30.444us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.540s 20.517us 5 5 100.00
lc_ctrl_csr_aliasing 1.610s 53.045us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 10.050s 61.090us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 18.950s 358.870us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.270s 34.767us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 5.970s 165.764us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 13.820s 339.595us 20 20 100.00
lc_errors 19 20 95.00
lc_ctrl_errors 13.440s 4942.014us 19 20 95.00
security_escalation 139 140 99.29
lc_ctrl_state_failure 13.820s 339.595us 20 20 100.00
lc_ctrl_prog_failure 5.970s 165.764us 20 20 100.00
lc_ctrl_errors 13.440s 4942.014us 19 20 95.00
lc_ctrl_security_escalation 13.540s 1105.624us 20 20 100.00
lc_ctrl_jtag_state_failure 60.740s 9730.414us 20 20 100.00
lc_ctrl_jtag_prog_failure 11.630s 1640.379us 20 20 100.00
lc_ctrl_jtag_errors 97.010s 9540.391us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_smoke 12.030s 1749.579us 20 20 100.00
lc_ctrl_jtag_state_post_trans 28.940s 1164.155us 20 20 100.00
lc_ctrl_jtag_prog_failure 11.630s 1640.379us 20 20 100.00
lc_ctrl_jtag_errors 97.010s 9540.391us 20 20 100.00
lc_ctrl_jtag_access 20.210s 1213.419us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 31.680s 2465.769us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 4.030s 145.737us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.380s 580.699us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 17.970s 1022.276us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 11.950s 632.814us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.300s 373.584us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 5.970s 586.541us 10 10 100.00
lc_ctrl_jtag_alert_test 2.620s 82.197us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 20.500s 2181.366us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.480s 15.178us 10 10 100.00
stress_all 8 10 80.00
lc_ctrl_stress_all 181.450s 15533.170us 8 10 80.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.700s 90.079us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 5.010s 217.353us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 5.010s 217.353us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.520s 18.958us 1 1 100.00
lc_ctrl_csr_rw 1.540s 20.517us 5 5 100.00
lc_ctrl_csr_aliasing 1.610s 53.045us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.720s 198.846us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.520s 18.958us 1 1 100.00
lc_ctrl_csr_rw 1.540s 20.517us 5 5 100.00
lc_ctrl_csr_aliasing 1.610s 53.045us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.720s 198.846us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 10.900s 965.927us 5 5 100.00
lc_ctrl_tl_intg_err 4.300s 119.125us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 4.300s 119.125us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 18.950s 358.870us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 13.820s 339.595us 20 20 100.00
lc_ctrl_sec_cm 10.900s 965.927us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 13.820s 339.595us 20 20 100.00
lc_ctrl_sec_cm 10.900s 965.927us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 13.820s 339.595us 20 20 100.00
lc_ctrl_sec_cm 10.900s 965.927us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 13.820s 339.595us 20 20 100.00
lc_ctrl_sec_cm 10.900s 965.927us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 13.820s 339.595us 20 20 100.00
lc_ctrl_sec_cm 10.900s 965.927us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 13.820s 339.595us 20 20 100.00
lc_ctrl_sec_cm 10.900s 965.927us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 13.820s 339.595us 20 20 100.00
lc_ctrl_sec_cm 10.900s 965.927us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 13.820s 339.595us 20 20 100.00
lc_ctrl_sec_cm 10.900s 965.927us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 13.540s 1105.624us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 10.050s 61.090us 20 20 100.00
lc_ctrl_jtag_state_post_trans 28.940s 1164.155us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 16.420s 859.917us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 16.420s 859.917us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 9.980s 2758.199us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 15.570s 2951.907us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 15.570s 2951.907us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 6 10 60.00
lc_ctrl_stress_all_with_rand_reset 92.630s 4903.154us 6 10 60.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 4 test runs
lc_ctrl_stress_all 41905284882060062743924357480237147760229805676899602642159377273764750421455 9232
UVM_INFO @ 1282992597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 49875424352513595612060781820031365259862540441299968526559565273004251280113 2348
UVM_INFO @ 286902510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 109795599300212080789951861053272179916146666621348932164007999928891393529614 1307
UVM_INFO @ 8407000766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 21979127051349772460303166535969589149076420092827170355355051198192502967900 12321
UVM_INFO @ 20774999116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
lc_ctrl_stress_all_with_rand_reset 90364267167272638248791951120129252909340767666032058747928986824824459641636 8059
UVM_INFO @ 4903154043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 98665785069663579740887269155446386107247372728302556103752157454587590141073 174
UVM_INFO @ 2358511347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 109557997340377847530261171073270446463838062360485575895868568199719701526553 4840
UVM_INFO @ 8154264969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---