Simulation Results: lc_ctrl/volatile_unlock_enabled

 
30/05/2026 15:09:44 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.40 %
  • code
  • 86.33 %
  • assert
  • 94.97 %
  • func
  • 95.91 %
  • line
  • 97.26 %
  • branch
  • 93.95 %
  • cond
  • 81.76 %
  • toggle
  • 89.54 %
  • FSM
  • 69.16 %
Validation stages
V1
100.00%
V2
99.53%
V2S
100.00%
V3
60.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 7.450s 173.892us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.890s 62.152us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 1.440s 14.770us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.450s 105.787us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.660s 69.320us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.770s 77.529us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 1.440s 14.770us 5 5 100.00
lc_ctrl_csr_aliasing 1.660s 69.320us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 7.580s 132.816us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 15.120s 362.548us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.300s 13.397us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 4.060s 110.219us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 14.240s 368.021us 20 20 100.00
lc_errors 19 20 95.00
lc_ctrl_errors 15.140s 1839.572us 19 20 95.00
security_escalation 139 140 99.29
lc_ctrl_state_failure 14.240s 368.021us 20 20 100.00
lc_ctrl_prog_failure 4.060s 110.219us 20 20 100.00
lc_ctrl_errors 15.140s 1839.572us 19 20 95.00
lc_ctrl_security_escalation 9.520s 587.292us 20 20 100.00
lc_ctrl_jtag_state_failure 61.160s 6354.511us 20 20 100.00
lc_ctrl_jtag_prog_failure 15.360s 1163.721us 20 20 100.00
lc_ctrl_jtag_errors 44.290s 2535.377us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_smoke 13.100s 12715.054us 20 20 100.00
lc_ctrl_jtag_state_post_trans 22.260s 970.328us 20 20 100.00
lc_ctrl_jtag_prog_failure 15.360s 1163.721us 20 20 100.00
lc_ctrl_jtag_errors 44.290s 2535.377us 20 20 100.00
lc_ctrl_jtag_access 21.150s 1688.739us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 25.500s 1211.088us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 4.090s 193.969us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.260s 195.679us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 30.360s 5275.113us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 22.260s 1257.254us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.890s 252.345us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 5.730s 1350.666us 10 10 100.00
lc_ctrl_jtag_alert_test 2.000s 358.008us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 16.600s 5723.067us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 1.360s 32.559us 10 10 100.00
stress_all 9 10 90.00
lc_ctrl_stress_all 209.730s 198748.182us 9 10 90.00
alert_test 10 10 100.00
lc_ctrl_alert_test 1.480s 45.834us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 4.120s 157.300us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 4.120s 157.300us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 0.890s 62.152us 1 1 100.00
lc_ctrl_csr_rw 1.440s 14.770us 5 5 100.00
lc_ctrl_csr_aliasing 1.660s 69.320us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.880s 172.460us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 0.890s 62.152us 1 1 100.00
lc_ctrl_csr_rw 1.440s 14.770us 5 5 100.00
lc_ctrl_csr_aliasing 1.660s 69.320us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.880s 172.460us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 7.320s 295.586us 5 5 100.00
lc_ctrl_tl_intg_err 4.950s 186.268us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 4.950s 186.268us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 15.120s 362.548us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 14.240s 368.021us 20 20 100.00
lc_ctrl_sec_cm 7.320s 295.586us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 14.240s 368.021us 20 20 100.00
lc_ctrl_sec_cm 7.320s 295.586us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 14.240s 368.021us 20 20 100.00
lc_ctrl_sec_cm 7.320s 295.586us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 14.240s 368.021us 20 20 100.00
lc_ctrl_sec_cm 7.320s 295.586us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 14.240s 368.021us 20 20 100.00
lc_ctrl_sec_cm 7.320s 295.586us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 14.240s 368.021us 20 20 100.00
lc_ctrl_sec_cm 7.320s 295.586us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 14.240s 368.021us 20 20 100.00
lc_ctrl_sec_cm 7.320s 295.586us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 14.240s 368.021us 20 20 100.00
lc_ctrl_sec_cm 7.320s 295.586us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 9.520s 587.292us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 7.580s 132.816us 20 20 100.00
lc_ctrl_jtag_state_post_trans 22.260s 970.328us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 12.810s 3542.697us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 12.810s 3542.697us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 14.040s 1366.740us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 10.310s 443.105us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 10.310s 443.105us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 6 10 60.00
lc_ctrl_stress_all_with_rand_reset 106.390s 95181.585us 6 10 60.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
lc_ctrl_stress_all_with_rand_reset 73848183735261690232915079682717855446528703386253466984504799946837416459751 442
UVM_INFO @ 6512672425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 32311796848890542244237173028364153646854718004026774004113463594144629838602 522
UVM_INFO @ 5720306622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 17530749572382144378253595208583279256380968337881408680988824424131131793426 5728
UVM_INFO @ 2956093902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 100001575346843756676784599374315103733639479959942007351272938529526399732414 5985
UVM_INFO @ 12641573975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 2 test runs
lc_ctrl_stress_all 27420824789153210406854513958518766934933362405022913629378866637062295914335 4945
UVM_INFO @ 2864502028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 14476172235090332679011498993125184378855842252605791781839443486119391749053 3750
UVM_INFO @ 1912480801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---