Simulation Results: otbn

 
30/05/2026 15:09:44 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 98.27 %
  • code
  • 96.80 %
  • assert
  • 98.00 %
  • func
  • 100.00 %
  • block
  • 99.53 %
  • line
  • 99.64 %
  • branch
  • 93.99 %
  • toggle
  • 93.55 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.55%
V2S
96.96%
V3
10.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 37.000s 216.447us 1 1 100.00
single_binary 100 100 100.00
otbn_single 111.000s 501.180us 100 100 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 37.000s 21.640us 1 1 100.00
csr_rw 5 5 100.00
otbn_csr_rw 37.000s 44.420us 5 5 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 39.000s 126.952us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 37.000s 130.733us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
otbn_csr_mem_rw_with_rand_reset 39.000s 102.441us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otbn_csr_rw 37.000s 44.420us 5 5 100.00
otbn_csr_aliasing 37.000s 130.733us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 167.000s 8895.027us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 60.000s 1192.713us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 56.000s 368.126us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 78.000s 384.508us 1 1 100.00
back_to_back 9 10 90.00
otbn_multi 168.000s 1422.123us 9 10 90.00
stress_all 9 10 90.00
otbn_stress_all 220.000s 1159.092us 9 10 90.00
lc_escalation 58 60 96.67
otbn_escalate 35.000s 34.607us 58 60 96.67
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 26.000s 32.255us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 34.000s 41.564us 10 10 100.00
alert_test 10 10 100.00
otbn_alert_test 38.000s 60.071us 10 10 100.00
intr_test 10 10 100.00
otbn_intr_test 37.000s 193.790us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otbn_tl_errors 28.000s 113.298us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otbn_tl_errors 28.000s 113.298us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otbn_csr_hw_reset 37.000s 21.640us 1 1 100.00
otbn_csr_rw 37.000s 44.420us 5 5 100.00
otbn_csr_aliasing 37.000s 130.733us 1 1 100.00
otbn_same_csr_outstanding 34.000s 18.432us 5 5 100.00
tl_d_partial_access 12 12 100.00
otbn_csr_hw_reset 37.000s 21.640us 1 1 100.00
otbn_csr_rw 37.000s 44.420us 5 5 100.00
otbn_csr_aliasing 37.000s 130.733us 1 1 100.00
otbn_same_csr_outstanding 34.000s 18.432us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 38.000s 64.949us 10 10 100.00
otbn_dmem_err 40.000s 33.852us 15 15 100.00
internal_integrity 16 17 94.12
otbn_alu_bignum_mod_err 77.000s 313.157us 5 5 100.00
otbn_controller_ispr_rdata_err 38.000s 47.334us 5 5 100.00
otbn_mac_bignum_acc_err 37.000s 195.887us 5 5 100.00
otbn_urnd_err 28.000s 13.317us 1 2 50.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 39.000s 96.456us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 35.000s 26.079us 2 2 100.00
otbn_non_sec_partial_wipe 7 10 70.00
otbn_partial_wipe 35.000s 46.721us 7 10 70.00
tl_intg_err 30 30 100.00
otbn_sec_cm 782.000s 6963.269us 5 5 100.00
otbn_tl_intg_err 45.000s 116.764us 25 25 100.00
passthru_mem_tl_intg_err 4 5 80.00
otbn_passthru_mem_tl_intg_err 85.000s 811.613us 4 5 80.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 782.000s 6963.269us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 782.000s 6963.269us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 37.000s 216.447us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 40.000s 33.852us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 38.000s 64.949us 10 10 100.00
sec_cm_bus_integrity 25 25 100.00
otbn_tl_intg_err 45.000s 116.764us 25 25 100.00
sec_cm_controller_fsm_global_esc 58 60 96.67
otbn_escalate 35.000s 34.607us 58 60 96.67
sec_cm_controller_fsm_local_esc 40 40 100.00
otbn_imem_err 38.000s 64.949us 10 10 100.00
otbn_dmem_err 40.000s 33.852us 15 15 100.00
otbn_zero_state_err_urnd 26.000s 32.255us 5 5 100.00
otbn_illegal_mem_acc 39.000s 96.456us 5 5 100.00
otbn_sec_cm 782.000s 6963.269us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 782.000s 6963.269us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 111.000s 501.180us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 38.000s 64.949us 10 10 100.00
otbn_dmem_err 40.000s 33.852us 15 15 100.00
otbn_zero_state_err_urnd 26.000s 32.255us 5 5 100.00
otbn_illegal_mem_acc 39.000s 96.456us 5 5 100.00
otbn_sec_cm 782.000s 6963.269us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 782.000s 6963.269us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 58 60 96.67
otbn_escalate 35.000s 34.607us 58 60 96.67
sec_cm_start_stop_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 38.000s 64.949us 10 10 100.00
otbn_dmem_err 40.000s 33.852us 15 15 100.00
otbn_zero_state_err_urnd 26.000s 32.255us 5 5 100.00
otbn_illegal_mem_acc 39.000s 96.456us 5 5 100.00
otbn_sec_cm 782.000s 6963.269us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 782.000s 6963.269us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 111.000s 501.180us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 37.000s 14.333us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 35.000s 23.531us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 54.000s 108.253us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 54.000s 108.253us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 9 10 90.00
otbn_rf_base_intg_err 43.000s 32.186us 9 10 90.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 782.000s 6963.269us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 782.000s 6963.269us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 37.000s 56.501us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 782.000s 6963.269us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 782.000s 6963.269us 5 5 100.00
sec_cm_loop_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 42.000s 373.726us 4 5 80.00
sec_cm_call_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 42.000s 373.726us 4 5 80.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 33.000s 37.241us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 111.000s 501.180us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 111.000s 501.180us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 111.000s 501.180us 100 100 100.00
sec_cm_write_mem_integrity 9 10 90.00
otbn_multi 168.000s 1422.123us 9 10 90.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 111.000s 501.180us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 111.000s 501.180us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 32.000s 29.877us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 111.000s 501.180us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 782.000s 6963.269us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 10 10.00
otbn_stress_all_with_rand_reset 289.000s 1909.678us 1 10 10.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 35.000s 77.665us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 7 test runs
otbn_stress_all_with_rand_reset 44700089425885084065330266288437135500678808914553125061684817170370167866626 573
UVM_INFO @ 1909677899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 17273477757325240285766871649271024868483991257337538597057131742263442460164 159
UVM_INFO @ 135142662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 37236946827695667992836648531581595648998102277036758915351733931247413643412 161
UVM_INFO @ 214579398 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 47844620422108253156320189735273300751424846406914746522691698997629839769067 340
UVM_INFO @ 926895845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 111982315471270758565824299334357900879159799291620054302107906166190247248721 169
UVM_INFO @ 128752634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 16478137741339636645851778341984257016817879462737994758085811592570045735964 257
UVM_INFO @ 326953077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 61670847662425984842022463125455566156944047504724143549817184054942873432036 194
UVM_INFO @ 645849144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status 3 test runs
otbn_urnd_err 93088049877842243993584550179029114945817207061861260860860590889088088392522 114
UVM_INFO @ 16775042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_partial_wipe 37074871077375326680094692896076615722117960174831692879987652248280884427964 114
UVM_INFO @ 7681883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 1655278861451922653411468257862007777523226064413544562585598496699933875600 108
UVM_INFO @ 9192700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sim_*/tb.sv,292): Assertion MatchingStatus_A has failed 2 test runs
otbn_partial_wipe 58266708869949927605611399012605285906487115311211084225717465841903199624328 107
UVM_ERROR @ 7695509 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 7695509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_partial_wipe 24033346892412978764910114253189009143116167981695325632899113327302922289204 110
UVM_ERROR @ 15338588 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
UVM_INFO @ 15338588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 2 test runs
otbn_stack_addr_integ_chk 62668557866833442241981006615155362687718433408540308549437380890278701895694 120
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 10449567 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 10449567 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 10449567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 99334317794212544310696051297864668066248427929832648208853698679367678795854 114
UVM_ERROR @ 13080460 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 13080460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 10531756613914139480529427638016671581902095034829455833851391709709824996701 169
UVM_INFO @ 2236598081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 1 test run
otbn_rf_base_intg_err 45904047559309334028142320017639258136046434306644800462272420248510450072114 120
UVM_INFO @ 1804109395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 81152011024493514009204719957488536276104029269832031062789432081893330989820 148
UVM_INFO @ 6198835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. 1 test run
otbn_passthru_mem_tl_intg_err 76108219848419977347866008336846235368776403349213628666333106467421832621851 101
UVM_INFO @ 58100567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 1 test run
otbn_stress_all 91520951309835889634429536684511456011668591578691671228772897700213097591875 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_multi 88281208280564973027882459137203308118593820922943811486717668632374862847864 187
UVM_INFO @ 256044941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---