Simulation Results: otp_ctrl

 
30/05/2026 15:09:44 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.33 %
  • code
  • 86.23 %
  • assert
  • 95.52 %
  • func
  • 92.23 %
  • line
  • 90.30 %
  • branch
  • 86.80 %
  • cond
  • 94.10 %
  • toggle
  • 95.87 %
  • FSM
  • 64.06 %
Validation stages
V1
96.15%
V2
95.12%
V2S
94.85%
V3
27.72%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.580s 53.013us 1 1 100.00
smoke 10 10 100.00
otp_ctrl_smoke 8.670s 1894.375us 10 10 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.260s 352.916us 1 1 100.00
csr_rw 5 5 100.00
otp_ctrl_csr_rw 2.170s 168.092us 5 5 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.280s 261.783us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 5.460s 182.043us 1 1 100.00
csr_mem_rw_with_rand_reset 4 5 80.00
otp_ctrl_csr_mem_rw_with_rand_reset 4.410s 1728.456us 4 5 80.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otp_ctrl_csr_rw 2.170s 168.092us 5 5 100.00
otp_ctrl_csr_aliasing 5.460s 182.043us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.720s 48.653us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.480s 563.814us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 13.650s 310.605us 1 1 100.00
init_fail 300 300 100.00
otp_ctrl_init_fail 8.060s 2365.505us 300 300 100.00
partition_check 38 60 63.33
otp_ctrl_background_chks 49.070s 28179.710us 10 10 100.00
otp_ctrl_check_fail 24.160s 14112.314us 28 50 56.00
regwen_during_otp_init 30 30 100.00
otp_ctrl_regwen 10.530s 388.730us 30 30 100.00
partition_lock 29 30 96.67
otp_ctrl_dai_lock 69.010s 10243.854us 29 30 96.67
interface_key_check 10 10 100.00
otp_ctrl_parallel_key_req 50.710s 8576.164us 10 10 100.00
lc_interactions 209 210 99.52
otp_ctrl_parallel_lc_req 21.730s 900.700us 10 10 100.00
otp_ctrl_parallel_lc_esc 55.650s 10014.266us 199 200 99.50
otp_dai_errors 10 10 100.00
otp_ctrl_dai_errs 25.260s 3819.260us 10 10 100.00
otp_macro_errors 0 10 0.00
otp_ctrl_macro_errs 92.940s 14581.663us 0 10 0.00
test_access 9 10 90.00
otp_ctrl_test_access 73.200s 10270.150us 9 10 90.00
stress_all 9 10 90.00
otp_ctrl_stress_all 304.190s 146924.669us 9 10 90.00
intr_test 10 10 100.00
otp_ctrl_intr_test 2.240s 566.572us 10 10 100.00
alert_test 10 10 100.00
otp_ctrl_alert_test 3.670s 512.195us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otp_ctrl_tl_errors 6.500s 339.379us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otp_ctrl_tl_errors 6.500s 339.379us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otp_ctrl_csr_hw_reset 2.260s 352.916us 1 1 100.00
otp_ctrl_csr_rw 2.170s 168.092us 5 5 100.00
otp_ctrl_csr_aliasing 5.460s 182.043us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.240s 330.773us 5 5 100.00
tl_d_partial_access 12 12 100.00
otp_ctrl_csr_hw_reset 2.260s 352.916us 1 1 100.00
otp_ctrl_csr_rw 2.170s 168.092us 5 5 100.00
otp_ctrl_csr_aliasing 5.460s 182.043us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.240s 330.773us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
otp_ctrl_sec_cm 233.540s 177550.884us 5 5 100.00
tl_intg_err 30 30 100.00
otp_ctrl_sec_cm 233.540s 177550.884us 5 5 100.00
otp_ctrl_tl_intg_err 36.270s 20180.676us 25 25 100.00
prim_count_check 5 5 100.00
otp_ctrl_sec_cm 233.540s 177550.884us 5 5 100.00
prim_fsm_check 5 5 100.00
otp_ctrl_sec_cm 233.540s 177550.884us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
otp_ctrl_tl_intg_err 36.270s 20180.676us 25 25 100.00
sec_cm_secret_mem_scramble 10 10 100.00
otp_ctrl_smoke 8.670s 1894.375us 10 10 100.00
sec_cm_part_mem_digest 10 10 100.00
otp_ctrl_smoke 8.670s 1894.375us 10 10 100.00
sec_cm_dai_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 233.540s 177550.884us 5 5 100.00
sec_cm_kdi_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 233.540s 177550.884us 5 5 100.00
sec_cm_lci_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 233.540s 177550.884us 5 5 100.00
sec_cm_part_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 233.540s 177550.884us 5 5 100.00
sec_cm_scrmbl_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 233.540s 177550.884us 5 5 100.00
sec_cm_timer_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 233.540s 177550.884us 5 5 100.00
sec_cm_dai_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 233.540s 177550.884us 5 5 100.00
sec_cm_kdi_seed_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 233.540s 177550.884us 5 5 100.00
sec_cm_kdi_entropy_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 233.540s 177550.884us 5 5 100.00
sec_cm_lci_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 233.540s 177550.884us 5 5 100.00
sec_cm_part_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 233.540s 177550.884us 5 5 100.00
sec_cm_scrmbl_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 233.540s 177550.884us 5 5 100.00
sec_cm_timer_integ_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 233.540s 177550.884us 5 5 100.00
sec_cm_timer_cnsty_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 233.540s 177550.884us 5 5 100.00
sec_cm_timer_lfsr_redun 5 5 100.00
otp_ctrl_sec_cm 233.540s 177550.884us 5 5 100.00
sec_cm_dai_fsm_local_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 55.650s 10014.266us 199 200 99.50
otp_ctrl_sec_cm 233.540s 177550.884us 5 5 100.00
sec_cm_lci_fsm_local_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 55.650s 10014.266us 199 200 99.50
sec_cm_kdi_fsm_local_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 55.650s 10014.266us 199 200 99.50
sec_cm_part_fsm_local_esc 199 210 94.76
otp_ctrl_parallel_lc_esc 55.650s 10014.266us 199 200 99.50
otp_ctrl_macro_errs 92.940s 14581.663us 0 10 0.00
sec_cm_scrmbl_fsm_local_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 55.650s 10014.266us 199 200 99.50
sec_cm_timer_fsm_local_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 55.650s 10014.266us 199 200 99.50
otp_ctrl_sec_cm 233.540s 177550.884us 5 5 100.00
sec_cm_dai_fsm_global_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 55.650s 10014.266us 199 200 99.50
otp_ctrl_sec_cm 233.540s 177550.884us 5 5 100.00
sec_cm_lci_fsm_global_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 55.650s 10014.266us 199 200 99.50
sec_cm_kdi_fsm_global_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 55.650s 10014.266us 199 200 99.50
sec_cm_part_fsm_global_esc 199 210 94.76
otp_ctrl_parallel_lc_esc 55.650s 10014.266us 199 200 99.50
otp_ctrl_macro_errs 92.940s 14581.663us 0 10 0.00
sec_cm_scrmbl_fsm_global_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 55.650s 10014.266us 199 200 99.50
sec_cm_timer_fsm_global_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 55.650s 10014.266us 199 200 99.50
otp_ctrl_sec_cm 233.540s 177550.884us 5 5 100.00
sec_cm_part_data_reg_integrity 300 300 100.00
otp_ctrl_init_fail 8.060s 2365.505us 300 300 100.00
sec_cm_part_data_reg_bkgn_chk 28 50 56.00
otp_ctrl_check_fail 24.160s 14112.314us 28 50 56.00
sec_cm_part_mem_regren 29 30 96.67
otp_ctrl_dai_lock 69.010s 10243.854us 29 30 96.67
sec_cm_part_mem_sw_unreadable 29 30 96.67
otp_ctrl_dai_lock 69.010s 10243.854us 29 30 96.67
sec_cm_part_mem_sw_unwritable 29 30 96.67
otp_ctrl_dai_lock 69.010s 10243.854us 29 30 96.67
sec_cm_lc_part_mem_sw_noaccess 29 30 96.67
otp_ctrl_dai_lock 69.010s 10243.854us 29 30 96.67
sec_cm_access_ctrl_mubi 29 30 96.67
otp_ctrl_dai_lock 69.010s 10243.854us 29 30 96.67
sec_cm_token_valid_ctrl_mubi 10 10 100.00
otp_ctrl_smoke 8.670s 1894.375us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 29 30 96.67
otp_ctrl_dai_lock 69.010s 10243.854us 29 30 96.67
sec_cm_test_bus_lc_gated 10 10 100.00
otp_ctrl_smoke 8.670s 1894.375us 10 10 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 233.540s 177550.884us 5 5 100.00
sec_cm_direct_access_config_regwen 30 30 100.00
otp_ctrl_regwen 10.530s 388.730us 30 30 100.00
sec_cm_check_trigger_config_regwen 10 10 100.00
otp_ctrl_smoke 8.670s 1894.375us 10 10 100.00
sec_cm_check_config_regwen 10 10 100.00
otp_ctrl_smoke 8.670s 1894.375us 10 10 100.00
sec_cm_macro_mem_integrity 0 10 0.00
otp_ctrl_macro_errs 92.940s 14581.663us 0 10 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 15.470s 7539.445us 1 1 100.00
stress_all_with_rand_reset 27 100 27.00
otp_ctrl_stress_all_with_rand_reset 3600.120s 0.000us 27 100 27.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 43 test runs
otp_ctrl_macro_errs 108151979298889290418780101081367454288207100576718867149334070100134646637078 4022
UVM_INFO @ 1822781981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 113089270535108036389381227114938807805108386382456196756638804981688907298096 157
UVM_INFO @ 38425540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 33271110016573118809862160407338032629717183646308795903196299653857715195351 1403
UVM_INFO @ 241401376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 66108175732507756295192877133040178003981773406789464422808387982441853512272 39628
UVM_INFO @ 9327758852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 7008933722999818801010409414472747923693527825081792239230617271932034803236 6569
UVM_INFO @ 14581662849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 70358408533807064330051779969105834359175547725086492985424320215170238240714 1693
UVM_INFO @ 176112155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 83326296007749910897682083312193750768225724723042106908428607450502211957218 2167
UVM_INFO @ 355719916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 73086434947880195804430440111656275308963000184963749670435103674118584317518 8979
UVM_INFO @ 5299258959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 115148238041989428438859273365008826479298274379306180796875059066082820824395 1366
UVM_INFO @ 594143129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 49590175135717089307474245364193572004996333207477352381726452242918874255672 1786
UVM_INFO @ 130276038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 35642006867607679193978898620132591501360860119748053935052206176288364393775 8898
UVM_INFO @ 1994512842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 86090233470084071068995759239831046810317524423147545187447903526228675931460 7820
UVM_INFO @ 2772021867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 48823568163558701187370248979369358564233893148176624304633420131784482336679 13925
UVM_INFO @ 25905075804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 100678470819018266281776650258937925604653164313487092192267844516078699845110 501
UVM_INFO @ 133878846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 65278737125663802581169794288647841128602808503912471519952240566193485830552 3675
UVM_INFO @ 1320849414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 2708638058557935828672902289056321926595631546658352086540198846606286484387 3507
UVM_INFO @ 211229244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 103061482179338935687749425130393862724186235715318222646072995539470828084904 11242
UVM_INFO @ 1957790181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 47280651071851248853291478409033921693536362606143973246328536618602504849917 3678
UVM_INFO @ 1149518384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 45196053139918486726278266479843715419791956858981926955359216824290273329118 1242
UVM_INFO @ 300101820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 19341630236088519049853692702718475016143740409036753595530463845448869223993 1595
UVM_INFO @ 4311160679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 35726867506158960071501550300605324679917644000180284234957287685833624679728 6006
UVM_INFO @ 6745400158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 20951550704854376884576177229934348774057123136619526502077567279538543528913 11467
UVM_INFO @ 1347853308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 107005874573695277904510165345098841718567709436250608784302796419796845645287 2498
UVM_INFO @ 368882921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 16621834611073476222658483731070282516513431378261249615240781273169596312947 927
UVM_INFO @ 182600766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 71124893320782778858496713054290880155864494323359449664451468380551154933490 163
UVM_INFO @ 29076474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 40350539473527911363534042530553761241254204741687526918436624152789190455081 7039
UVM_INFO @ 2370083642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 40213779612554950815109053880396974894501111443311907106822363326737194692822 1287
UVM_INFO @ 329200881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 9782922466711898503972567474546355792232115712140863008743661016769723697578 5535
UVM_INFO @ 6843686012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 50935997008380846508240014500308779170326670970946853741776345317360303533956 7442
UVM_INFO @ 527080597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 80699940455969945505136967725406763977396986237895683358488823548431095045432 2524
UVM_INFO @ 4135753628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 104905301084492923970859951601259748288648269407265619630918636485205946739089 3437
UVM_INFO @ 4567985230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 81146197320515299137328231783322416807965267411549326565395059990346965681711 1283
UVM_INFO @ 170864319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 57395248385517551795690579769715764351099583737231756393566159283126471465449 866
UVM_INFO @ 320261631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 112287745572599530369213409958718118719069098067696522760114642940060102996757 771
UVM_INFO @ 45672059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 6574514229398491637548390151281363238849791002105444268747551057860440529750 4608
UVM_INFO @ 6822784615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 48425966065604448885425458242814579431951327185560260418799060599930546930556 9810
UVM_INFO @ 2173336865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 96415600321975320832605140023920037021526085931629419919925648044157682827305 1598
UVM_INFO @ 1159756613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 75711581366754436020723948774290778272018522226109396239993748556051284553412 11129
UVM_INFO @ 1440990493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 21905949759634556935109042705282522502057615000641904098591020829820005952988 645
UVM_INFO @ 75227702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 46628692104211355968070995699070953215994694423156961158125692869712003407084 177
UVM_INFO @ 34065402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 11134080611908191335309513076165075453336361359742493012127199111612450263492 169
UVM_INFO @ 76855084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 47147114166778787509806898265653826290445291202738684500706153807418476017799 19679
UVM_INFO @ 16948582797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 68898024500965523879066841673548568642498055868256371954078015814874244084354 209
UVM_INFO @ 44956723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1825) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 28 test runs
otp_ctrl_stress_all_with_rand_reset 21021346755395146476066594186557165596849467348353243110111344135944927525062 10175
UVM_INFO @ 2252733568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 5851763445605259897487202156864759381511445197531882204521501006477043453487 92
UVM_INFO @ 27739262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 86810378422516155490177133200037117860149743072167567746353445320875935975339 93
UVM_INFO @ 56134796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 68343238570453986530054327304934531603666079602688678112488196541093083511681 507
UVM_INFO @ 121993253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 56006491700981549526365500958403490093398658318449071359692758512329635443298 92
UVM_INFO @ 71372015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 90505333163188789350024177266571867947536490576634347110725538733526825184197 92
UVM_INFO @ 29030501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 63488389400902609270405530252333643216345570539080637157058783335740742258171 148
UVM_INFO @ 54411022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 11989829144541307369596887512022388523296468466102592313577105958281097254686 92
UVM_INFO @ 52690333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 104277559887721313466220065322252356207290502304539473333265284434957616387935 12421
UVM_INFO @ 707689842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 35121129084231465847713498819044497155828660144433201763535690358783351934248 10318
UVM_INFO @ 39924882778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 115089986353262720098491823140396486777232318114645540332248446813701473574809 1582
UVM_INFO @ 419473373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 5987200951863630875669602027565361915497944196378786426728730761583102102567 148
UVM_INFO @ 497095069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 74699032477547686766176558081875636607854192348761439586261305888489660303151 23530
UVM_INFO @ 4833042892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 82027838543962900760913795334152181935453973783429111877156609871720824999684 20887
UVM_INFO @ 3022344206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 55297350320830997339413087039776943496323721558491229267614072614621011478368 5990
UVM_INFO @ 15307692508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 78613782449975067084350859564674194801511518791573261757099870952003404088157 93
UVM_INFO @ 55500108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 94148661477975526889267971400995020978762800965807872836556857569162983851237 92
UVM_INFO @ 32869243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 24816393897937837050241654366626699814919888584631219467244776781503456067260 34980
UVM_INFO @ 1235066470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 100924740536053624386642104827795034516102852164730595118193448419200926030694 9168
UVM_INFO @ 6209523957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 69577368232499383498726553612711260831384159815628307226450593211851696442019 10961
UVM_INFO @ 12926795226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 49428351513131516738963649279424483160834565338068441947289062461324649406667 92
UVM_INFO @ 37599719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 26660706156542126240339939142101114652579374655868769335313840987355308994358 10069
UVM_INFO @ 550584116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 2292606841993928955000891229786266095461802298936428758612593634358264300255 1520
UVM_INFO @ 3223243513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 25637582923061007814041398224098608077780071006334675700906974552502390879988 36438
UVM_INFO @ 30118314376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 14464345456723232527845051094598881279881931578327257908158847132843835567392 72018
UVM_INFO @ 25152398402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 75893826482803924845150237708169085258204402255127804022338689826512383540088 7352
UVM_INFO @ 654091583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 36399807281074008596257557557449624490839957895335985453462780302867979710598 8023
UVM_INFO @ 699587130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 70386595572129943150679113587557678472500144404406639319211086780703595535809 17011
UVM_INFO @ 611919691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 16 test runs
otp_ctrl_stress_all_with_rand_reset 107368991478935092808650364068181423491455527551020707443360056139713779499868 507
UVM_INFO @ 13444426900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 102893239723232360539259419139231207230211516573217440236841755656253773821089 4888
UVM_INFO @ 5053863046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 63514622538481198638309936935960582772015194856348491457933811098839365760644 9044
UVM_INFO @ 3298234203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 28253664625948187269652907543722813147987297683849400486442502423004212757147 8690
UVM_INFO @ 24368470203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 71147857357524491913700265736247235440979192830761443839780371120204568319800 4801
UVM_INFO @ 1446807737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 62646812363176929926676954412932664800379983780214599335292169870174415847690 5115
UVM_INFO @ 1038686614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 105198358493260345139349700820934724780698076683285403022153804511433272742418 5417
UVM_INFO @ 21629951031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 50296799200709168074928510111267195149198014857950501717583412936298205122148 6459
UVM_INFO @ 3288106889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 1253558974161273998377812043707868663093981728312872279478030909327577125145 1018
UVM_INFO @ 2443619494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 45716233979321431201043633612704009837889470064271972928934947590545521317189 13050
UVM_INFO @ 26781911729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 95906347124682009083245205574945677292872550627935013270489430215883966073533 5371
UVM_INFO @ 28420011614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 31272067412137604411007242213901043067525482152263827801162652713290776933649 5994
UVM_INFO @ 20776811055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 29132712907906565319214557779686997339631135214364247959230527301426489619783 9203
UVM_INFO @ 31960325282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 111708843643062161609487624857817971194686683183041800315325489253466332292046 7878
UVM_INFO @ 994641529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 27419628122869707983272170195310858786992655738784252517540245639758811062085 5046
UVM_INFO @ 15801038670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 32918228558227732601125347903682764137846072391717016292783532648747074387458 149
UVM_INFO @ 76253953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 7 test runs
otp_ctrl_stress_all_with_rand_reset 88426184647448084355462719401776190021706391716482383027968058667206018247483 4939
UVM_INFO @ 23523187183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 20000117173038470464599897078016050720841430981122162153727591474018384517318 92
UVM_INFO @ 36723010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 35438365161538675006770080226718547291068046935780255953644165475471944904747 93
UVM_INFO @ 53791128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 62902446106440573533835373032041631024822104276244279749030423196435889520533 92
UVM_INFO @ 57352560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 61589207620950288361452223586694570629634012886406665892639458504804733055884 33715
UVM_INFO @ 2477125303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 97145293072606475027134199943112034935459393208065479622520411883452705904924 198
UVM_INFO @ 9147123985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 108722729742179325163596760135738887639807778384778910746624291796992678791790 16718
UVM_INFO @ 2336700608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch 4 test runs
otp_ctrl_stress_all_with_rand_reset 10877899993547402143020697050084809365555214925639183216125970154126794712047 5850
UVM_INFO @ 22901433106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 62034093946743331442994959992296216302267405004179669895133134659113758964299 409
UVM_INFO @ 3365784715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 7191117300780472915796612061972029667475634708138450912951026977194383981385 2200
UVM_INFO @ 27190694092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 6269642504045823119952677341092147743110148683551422407670891133369379053664 513
UVM_INFO @ 13579864034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(cio_test_en_o == *)' 2 test runs
otp_ctrl_csr_mem_rw_with_rand_reset 101605470420955643100002975492262371352092017493241170533505372922237859347184 93
UVM_ERROR @ 103561310 ps: (otp_ctrl_if.sv:297) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 103561310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 7298272782296366857736290930989437996686804312029255971808039935409314377245 5933
UVM_ERROR @ 11270826031 ps: (otp_ctrl_if.sv:297) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 11270826031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
otp_ctrl_stress_all_with_rand_reset 68969178214498404950180303422550640844582769070142162015221155261295251307289 6404
UVM_INFO @ 8565205061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 108424652579657044180629976935695727477959810283251510468260948126155340679785 8568
UVM_INFO @ 12701065362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen 2 test runs
otp_ctrl_stress_all_with_rand_reset 91133952641301057022339970593512306178813082625240707443356920014694146374931 8109
UVM_INFO @ 20312538034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 91871467761054333832115652122717212150145822347287796585814033157063007357515 6181
UVM_INFO @ 1239257237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [otp_ctrl_test_access_vseq] wait timeout occurred! 1 test run
otp_ctrl_test_access 71270160551102872636089717665893422064791693732201126813406232295941567786957 8937
UVM_INFO @ 10270149533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
otp_ctrl_stress_all_with_rand_reset 42764487061711816991554428244084922291125439013057677728314459507047528085580 None
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *f* rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 106749521232986879959452223870523724420267671447554410702846075358635086535735 96
UVM_INFO @ 8053161874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [otp_ctrl_dai_lock_vseq] wait timeout occurred! 1 test run
otp_ctrl_dai_lock 43316295732036805872787997767612741279929373745086433690244771628264379009900 2156
UVM_INFO @ 10243854028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 71683069945519616979646884703769047214970556768638363351830345350952467065043 7949
UVM_INFO @ 3868264298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [otp_ctrl_parallel_lc_esc_vseq] wait timeout occurred! 1 test run
otp_ctrl_parallel_lc_esc 87603065904198765394491934275509952889601085229577783156588544126191441678579 89
UVM_INFO @ 10014266133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---