| V1 |
|
100.00% |
| V2 |
|
81.32% |
| V2S |
|
100.00% |
| V3 |
|
4.00% |
| unmapped |
|
70.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 50 | 50 | 100.00 | |||
| pattgen_smoke | 6.000s | 171.326us | 50 | 50 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| pattgen_csr_hw_reset | 1.000s | 12.847us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| pattgen_csr_rw | 1.000s | 48.921us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| pattgen_csr_bit_bash | 2.000s | 175.570us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| pattgen_csr_aliasing | 1.000s | 51.294us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| pattgen_csr_mem_rw_with_rand_reset | 2.000s | 102.014us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| pattgen_csr_rw | 1.000s | 48.921us | 5 | 5 | 100.00 | |
| pattgen_csr_aliasing | 1.000s | 51.294us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| perf | 30 | 50 | 60.00 | |||
| pattgen_perf | 3601.000s | 0.000us | 30 | 50 | 60.00 | |
| cnt_rollover | 50 | 50 | 100.00 | |||
| cnt_rollover | 80.000s | 11434.640us | 50 | 50 | 100.00 | |
| error | 50 | 50 | 100.00 | |||
| pattgen_error | 2.000s | 49.946us | 50 | 50 | 100.00 | |
| stress_all | 22 | 50 | 44.00 | |||
| pattgen_stress_all | 10802.076s | 0.000us | 22 | 50 | 44.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| pattgen_alert_test | 2.000s | 16.336us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| pattgen_intr_test | 2.000s | 49.697us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| pattgen_tl_errors | 3.000s | 707.957us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| pattgen_tl_errors | 3.000s | 707.957us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| pattgen_csr_hw_reset | 1.000s | 12.847us | 1 | 1 | 100.00 | |
| pattgen_csr_rw | 1.000s | 48.921us | 5 | 5 | 100.00 | |
| pattgen_csr_aliasing | 1.000s | 51.294us | 1 | 1 | 100.00 | |
| pattgen_same_csr_outstanding | 2.000s | 14.326us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| pattgen_csr_hw_reset | 1.000s | 12.847us | 1 | 1 | 100.00 | |
| pattgen_csr_rw | 1.000s | 48.921us | 5 | 5 | 100.00 | |
| pattgen_csr_aliasing | 1.000s | 51.294us | 1 | 1 | 100.00 | |
| pattgen_same_csr_outstanding | 2.000s | 14.326us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| pattgen_tl_intg_err | 2.000s | 98.011us | 25 | 25 | 100.00 | |
| pattgen_sec_cm | 2.000s | 38.720us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| pattgen_tl_intg_err | 2.000s | 98.011us | 25 | 25 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 2 | 50 | 4.00 | |||
| pattgen_stress_all_with_rand_reset | 121.000s | 4884.252us | 2 | 50 | 4.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 35 | 50 | 70.00 | |||
| pattgen_inactive_level | 244.000s | 10022.841us | 35 | 50 | 70.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (cip_base_vseq.sv:1287) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 47 test runs | |||
| pattgen_stress_all_with_rand_reset | 44777235229705244879776625898949422884251768982619841634490238216728328124582 | 139 |
UVM_ERROR @ 675214809 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 675214809 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 675530601 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 1555739055473215462845289749644095416112697110137198736301459326172930396135 | 288 |
UVM_ERROR @ 7745258624 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 7745258624 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 5/5
UVM_INFO @ 7745550293 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 61548273458680303225268973694751498754377046362475117936140924157211626404304 | 218 |
UVM_ERROR @ 5079684930 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 5079684930 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/5
UVM_INFO @ 5080069550 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 75931137054167896310042433473741174017676742928149059533397480964830709955294 | 275 |
UVM_ERROR @ 4029538023 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 4029538023 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 5/5
UVM_INFO @ 4029704687 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 58317313463545772544792100064651680143950602102276396487759021759919702998274 | 240 |
UVM_ERROR @ 2682724427 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2682724427 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 5/10
UVM_INFO @ 2682861683 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 100275812028331236861669370575328970544003543429334876209296720264726491103408 | 166 |
UVM_ERROR @ 4687513450 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 4687513450 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 4687782684 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 45697183577850304377712614745797381639289614118381449715031671972745496624861 | 176 |
UVM_ERROR @ 1266992792 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1266992792 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 1267196872 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 40092464073685528643921285181422462790428183098984629266063144445203451984424 | 114 |
UVM_ERROR @ 1069904334 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1069904334 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1070224334 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 20891024029398401867847766741955346551290317378171718196631537110045459751981 | 146 |
UVM_ERROR @ 235365075 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 235365075 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 235505075 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 69073018411672045710326284313855464315668154161056823933371073655726173367602 | 136 |
UVM_ERROR @ 163011508 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 163011508 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 163114076 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 40175403314336930072305905883405452267848248382512882524646382921501709325680 | 124 |
UVM_ERROR @ 1497217889 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1497217889 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1497403937 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 78805136851576033829396005308775852120138618495796656559336105207833639771941 | 129 |
UVM_ERROR @ 932233073 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 932233073 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 932285158 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 35106622538206338082058292017921965573916955841033035334423325314770724555847 | 188 |
UVM_ERROR @ 1227846773 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1227846773 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/5
UVM_INFO @ 1227878024 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 23806338928822901593162161758339120822585036197112508897229974822337030648945 | 160 |
UVM_ERROR @ 9440311012 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 9440311012 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 9440849473 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 59304690386119854638743395872712361738704666211941343135747018989073464509458 | 115 |
UVM_ERROR @ 478889003 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 478889003 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 478941633 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 9553933960317264840156091271514363850255653759470423872509935103047310957207 | 116 |
UVM_ERROR @ 1333942685 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1333942685 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1334192687 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 69454225380040093096005109250588406800014403615929562889624044243928357064705 | 121 |
UVM_ERROR @ 1832046584 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1832046584 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1832251712 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 110650695384113993093796043273648694511438504235142591065639835812935717166752 | 196 |
UVM_ERROR @ 1174581471 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1174581471 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/5
UVM_INFO @ 1174675224 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 59132240922425764934677345403910259571270951189904175196344206527740162001063 | 219 |
UVM_ERROR @ 2389018244 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2389018244 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/10
UVM_INFO @ 2389181508 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 33703041301822505074279757040625161212066480212439858293580786540068334425466 | 142 |
UVM_ERROR @ 1247647755 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1247647755 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1247887755 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 57469072013609756679303262565163298302280054111690694788162800749734612540704 | 143 |
UVM_ERROR @ 1752904153 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1752904153 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 1753104153 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 94445175636023623846232609593128319808916375702980471635683713324513956268298 | 113 |
UVM_ERROR @ 109873799 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 109873799 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 109904411 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 13284162842617699757639017893004292018094967646182040192814551750175481890891 | 183 |
UVM_ERROR @ 2833009851 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2833009851 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/5
UVM_INFO @ 2833134852 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 22045527177302461467701387930088169609222894960220156660588440986085879172130 | 168 |
UVM_ERROR @ 5317621170 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 5317621170 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 5317901170 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 37961404322489956425854256514170047882424789599727207274557372975970353576900 | 113 |
UVM_ERROR @ 443585971 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 443585971 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 443785971 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 85965578018436241241358542743064366420255054767172367949179216508345961016392 | 133 |
UVM_ERROR @ 495441664 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 495441664 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 495483768 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 26724975448439333042627606675692840939253779748647131733950449927184500019202 | 161 |
UVM_ERROR @ 790440336 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 790440336 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 790480740 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 60045761066120728452069782220507236312484452913450591154494467914446252104557 | 273 |
UVM_ERROR @ 2708203226 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2708203226 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 2708285698 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 25460223775841954398759715687896165365746885366758327354144398377127724855655 | 115 |
UVM_ERROR @ 1738975178 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1738975178 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1739225180 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 108071053808507034743387549633710545070513371433690666475884849123430511887590 | 144 |
UVM_ERROR @ 146828551 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 146828551 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 146869787 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 70149400081080252265514133997277904961098439635244965934638171069420017617863 | 209 |
UVM_ERROR @ 7551173772 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 7551173772 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 7551298773 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 96151817660308679378659887232108261506763563804169977227805131185697286404822 | 188 |
UVM_ERROR @ 6448883274 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 6448883274 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 6449421735 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 39209062545184013773560991748166101436659045887555346543437590452083204878525 | 149 |
UVM_ERROR @ 465362133 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 465362133 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 465463143 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 43311407508126957885624154672209608290567417241539104950348000449159771628511 | 207 |
UVM_ERROR @ 762829638 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 762829638 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 762909638 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 107288490363770013754130749349021318803850593682558102684380470773366677939718 | 199 |
UVM_ERROR @ 799392656 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 799392656 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 799422656 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 87176314328245490838183230841521634422514424968884321798822980052300866968485 | 208 |
UVM_ERROR @ 1105132252 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1105132252 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/5
UVM_INFO @ 1105173488 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 26093426244278091346686350603130602940351663449333222085970744093281101228780 | 154 |
UVM_ERROR @ 1048542438 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1048542438 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 1048622438 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 47647187138121462217002586712413378124235977950659313811764647357975815336278 | 131 |
UVM_ERROR @ 1602519111 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1602519111 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1602727441 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 29655882627493708090206753888762060464940474824171111076774107352732085185246 | 259 |
UVM_ERROR @ 5759166724 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 5759166724 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 5759253680 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 36263581240835194964667722641664156805619493847287758325025724810823177731008 | 160 |
UVM_ERROR @ 796969070 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 796969070 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 797062823 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 42915429024968142050563042631543470789463979650371979325843838776067870085922 | 113 |
UVM_ERROR @ 110630932 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 110630932 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 110662183 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 96291910948623861330942956046548719778660768670526840273764762471791281875126 | 184 |
UVM_ERROR @ 5621084858 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 5621084858 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/5
UVM_INFO @ 5621364858 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 22610693831230240053414332925693944934967343967489820119192579229496402696027 | 136 |
UVM_ERROR @ 152489795 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 152489795 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 152511071 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 26344223176696930515870533639745940311858344847149209080988906574325818595314 | 265 |
UVM_ERROR @ 2054290593 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2054290593 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 5/10
UVM_INFO @ 2054330593 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 43138121682807828652242435237155729665743405707088755000611325608083528213868 | 113 |
UVM_ERROR @ 441083966 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 441083966 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 441403966 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 82478620899096838291097468967785763452230666402175252362586756212138826115979 | 123 |
UVM_ERROR @ 1933010470 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1933010470 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1933050470 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 6806739692502442763582820474092543569092426370336403148006313863686886009958 | 146 |
UVM_ERROR @ 20167159650 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 20167159650 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 20169159650 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: | 19 test runs | |||
| pattgen_stress_all | 27408950917659069551063360086473967550183402669511360207652269951224809025176 | 138 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11342
|
|
| pattgen_stress_all | 61522144743803225716835734384271108467853152555871733195941842861712653995910 | 144 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11399
|
|
| pattgen_stress_all | 52186585163694063819470257420647110438151256145133083197805384461953433838092 | 163 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11320
|
|
| pattgen_stress_all | 10062107296075760043042001846788007253765204235411471543959280290529343268689 | 152 |
--------------------------------------
Name Type Size Value
--------------------------------------
exp_item pattgen_item - @11319
|
|
| pattgen_stress_all | 69582711999745708620159340854845353244303317974659118061304349297659320425031 | 136 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11309
|
|
| pattgen_stress_all | 104387804402895082132778769856271043972352687130996619652880399605105068758323 | 147 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11232
|
|
| pattgen_stress_all | 40694907783516376195914003429920331866081753707037580176152184642970917034037 | 139 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11296
|
|
| pattgen_stress_all | 50671690950245336859361307551112681497361965281546375072977507103654859200071 | 135 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11231
|
|
| pattgen_stress_all | 91664171857483988573015502776351279540724538903085721369579566574955921595211 | 136 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11344
|
|
| pattgen_stress_all | 23880726155889902939779707195621924683387808224481113779423705682060324003138 | 141 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11327
|
|
| pattgen_stress_all | 67550460270334411497799774540651045671537737980840149225722870789181851302736 | 155 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11479
|
|
| pattgen_stress_all | 84103461126835911418634991592663751759509742358425399193233004843374355877302 | 130 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11300
|
|
| pattgen_stress_all | 75275654360943603949855558565275088672919653302467968824162459675505643719890 | 132 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11353
|
|
| pattgen_stress_all | 54384475001582072043411180618518428525143118511607438809944383740767166818081 | 157 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11215
|
|
| pattgen_stress_all | 78157748377926504032097766040089904868872202571144702746668732739894995568187 | 162 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11258
|
|
| pattgen_stress_all | 10879189875263283018271025181618769353093885806674145689904217366081295857209 | 149 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11371
|
|
| pattgen_stress_all | 5951122823236173788343435321105952480962552474811068000126623799967665045080 | 125 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11303
|
|
| pattgen_stress_all | 47258338061317399722942633564781129881381920745924775708316953144936994721911 | 130 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11310
|
|
| pattgen_stress_all | 15998838030646220423400692272147741920134768887954209094754461397170098950114 | 135 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11237
|
|
| Job timed out after * minutes | 18 test runs | |||
| pattgen_stress_all | 25220424661475402929327914688638639632110612537389339698626769532253090512265 | None | ||
| pattgen_perf | 62680710712196641835938234889767962674717055085214247937237624223884609955537 | None | ||
| pattgen_stress_all | 51238186765669526268451726543689699858643482224552953816315736319091320278591 | None | ||
| pattgen_stress_all | 17233244305185992739110250144798858596558899914937692680185215647214288007148 | None | ||
| pattgen_stress_all | 54043914641975436212488194423122737224317808350559920006298330134322118117915 | None | ||
| pattgen_stress_all | 16831080764903152237783033892173289880735850617149316748684114768990745480419 | None | ||
| pattgen_perf | 37690572196229703696462421667419154476391589539368459772184331693470198449274 | None | ||
| pattgen_perf | 50006596047652980859607578947268400798604753168081902729309009993493016231136 | None | ||
| pattgen_perf | 115585919510000729464730048280329457508358646953947963299611302491040646746254 | None | ||
| pattgen_stress_all | 77996523357213619167991402734755714149136465152296672705058577578540966568656 | None | ||
| pattgen_perf | 4855851196181721668534248598801229578322125903980801932548769023020082868428 | None | ||
| pattgen_perf | 102220054166637714522437263309259828887537101366929871941993097541733599276076 | None | ||
| pattgen_perf | 80575401085391945110232447630718108038912673876004336069700229246010233466742 | None | ||
| pattgen_perf | 88717766840167627474486687206094782678018002180371273442447506090197070555110 | None | ||
| pattgen_stress_all | 34935376412970632228317020131855001550422431644458975282066462908357731632723 | None | ||
| pattgen_stress_all | 21489130488273061815993281151499205775756105366174985593201972520410598310997 | None | ||
| pattgen_perf | 48926878836886117472530549242951627930040238659745301723650720387153340357804 | None | ||
| pattgen_stress_all | 87453478508935421484657759860323705569855933714337411728888361102844507769411 | None | ||
| UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | 11 test runs | |||
| pattgen_perf | 95807932855304325714355863052432570364735366384672288480596686782167427845058 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 93895152510415743806606005616319071154597864309474805051870359131692938163485 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 79526945524454310696363284238475242854553693788453520454581486584238112476746 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 15758052695202522163909504006077551878855524124705514773029373856383154346619 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 32379173839212311509023868666735505798404811556590460062344873045195800581817 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 59121308052220499876446124617646160472668811521523450575855726518344159942784 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 18576823344869612364923090830130152633117520869759425577372700090861895967255 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 79655228447357081487096369489401496669363404937341676848352915889504434509088 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 8897844179803447277354904008947512500533294422725890881587097619040636946502 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 27268676272073611692547451243397666796710052064849872733137912508545572745035 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 77067913728192799999135830029790160256933148402758628823327389901340979148425 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) | 3 test runs | |||
| pattgen_inactive_level | 106810637104556225443032573931248412033075979974782428681016806806816316261198 | 99 |
UVM_INFO @ 10016631531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 18935387332961819810679654500992484251414771064514974879208615269347311257950 | 99 |
UVM_INFO @ 10027298502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 75976268526951754855373832544678537263141057323943085631428817956882746857386 | 99 |
UVM_INFO @ 10024955699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) | 2 test runs | |||
| pattgen_inactive_level | 112664123103863348761165168989230352403978329845339389257828641473788999771310 | 99 |
UVM_INFO @ 10009057375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 68903153029613601148545883001119941906509401308035241854244981712788558375980 | 99 |
UVM_INFO @ 10014672203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) | 2 test runs | |||
| pattgen_inactive_level | 26883362713305186855571218208501271509973878129312894436813878080364547302331 | 99 |
UVM_INFO @ 10008536355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 114263118548259837219321293552370342152471981667373435781948542843322078869922 | 99 |
UVM_INFO @ 10015116493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) | 2 test runs | |||
| pattgen_inactive_level | 88257560106150067696864334216252965101459134809243553783890437033777758636216 | 99 |
UVM_INFO @ 10017964480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 57509956277523399958387294146943180968674600065060822126192633102291561859326 | 99 |
UVM_INFO @ 10010199866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) | 1 test run | |||
| pattgen_inactive_level | 82562651268687928420365319536146043859587694819144116435303669211748421927703 | 99 |
UVM_INFO @ 10261269036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) | 1 test run | |||
| pattgen_inactive_level | 59750997910288274240655381954023901944452994966098859478995343777339788173027 | 99 |
UVM_INFO @ 10007193792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) | 1 test run | |||
| pattgen_inactive_level | 60184871263422178348223638956039141060446046373079034607366946388850679713768 | 99 |
UVM_INFO @ 10022840513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) | 1 test run | |||
| pattgen_inactive_level | 11756035911489068812111235684582566199846612159952752464991160969952727745655 | 99 |
UVM_INFO @ 10045988939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) | 1 test run | |||
| pattgen_inactive_level | 64600499244992584177246502495064050265859791884564480811203334815301638253121 | 99 |
UVM_INFO @ 10060198358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard] | 1 test run | |||
| pattgen_stress_all_with_rand_reset | 40808298088401844609391395523694029512145825231884551031810177268130748765990 | 139 |
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) | 1 test run | |||
| pattgen_inactive_level | 95681046291708990251208761537251403574494613317607089580631619085870140896485 | 99 |
UVM_INFO @ 10026108687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|