Simulation Results: pwrmgr

 
30/05/2026 15:09:44 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.51 %
  • code
  • 97.57 %
  • assert
  • 98.96 %
  • func
  • 99.01 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 96.75 %
  • toggle
  • 99.62 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
94.16%
V2S
100.00%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
pwrmgr_smoke 1.080s 25.530us 10 10 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 1.020s 31.920us 1 1 100.00
csr_rw 5 5 100.00
pwrmgr_csr_rw 1.030s 49.878us 5 5 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 3.580s 1190.071us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 1.250s 31.289us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.770s 69.486us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
pwrmgr_csr_rw 1.030s 49.878us 5 5 100.00
pwrmgr_csr_aliasing 1.250s 31.289us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 10 10 100.00
pwrmgr_wakeup 1.600s 305.638us 10 10 100.00
control_clks 10 10 100.00
pwrmgr_wakeup 1.600s 305.638us 10 10 100.00
aborted_low_power 20 20 100.00
pwrmgr_aborted_low_power 1.500s 37.536us 10 10 100.00
pwrmgr_lowpower_invalid 1.120s 43.467us 10 10 100.00
reset 15 20 75.00
pwrmgr_reset 4.570s 1000.000us 8 10 80.00
pwrmgr_reset_invalid 1.360s 102.976us 7 10 70.00
main_power_glitch_reset 8 10 80.00
pwrmgr_reset 4.570s 1000.000us 8 10 80.00
reset_wakeup_race 10 10 100.00
pwrmgr_wakeup_reset 1.490s 190.708us 10 10 100.00
lowpower_wakeup_race 10 10 100.00
pwrmgr_lowpower_wakeup_race 1.330s 309.638us 10 10 100.00
disable_rom_integrity_check 8 10 80.00
pwrmgr_disable_rom_integrity_check 1.780s 1000.000us 8 10 80.00
stress_all 9 10 90.00
pwrmgr_stress_all 22.340s 10063.923us 9 10 90.00
intr_test 10 10 100.00
pwrmgr_intr_test 1.010s 23.059us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
pwrmgr_tl_errors 3.110s 635.855us 25 25 100.00
tl_d_illegal_access 25 25 100.00
pwrmgr_tl_errors 3.110s 635.855us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
pwrmgr_csr_hw_reset 1.020s 31.920us 1 1 100.00
pwrmgr_csr_rw 1.030s 49.878us 5 5 100.00
pwrmgr_csr_aliasing 1.250s 31.289us 1 1 100.00
pwrmgr_same_csr_outstanding 1.090s 78.541us 5 5 100.00
tl_d_partial_access 12 12 100.00
pwrmgr_csr_hw_reset 1.020s 31.920us 1 1 100.00
pwrmgr_csr_rw 1.030s 49.878us 5 5 100.00
pwrmgr_csr_aliasing 1.250s 31.289us 1 1 100.00
pwrmgr_same_csr_outstanding 1.090s 78.541us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
pwrmgr_tl_intg_err 2.300s 214.510us 25 25 100.00
pwrmgr_sec_cm 3.140s 674.940us 5 5 100.00
prim_count_check 5 5 100.00
pwrmgr_sec_cm 3.140s 674.940us 5 5 100.00
prim_fsm_check 5 5 100.00
pwrmgr_sec_cm 3.140s 674.940us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
pwrmgr_tl_intg_err 2.300s 214.510us 25 25 100.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.560s 710.727us 10 10 100.00
sec_cm_rom_ctrl_intersig_mubi 10 10 100.00
pwrmgr_wakeup_reset 1.490s 190.708us 10 10 100.00
sec_cm_rstmgr_intersig_mubi 10 10 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 1.410s 93.153us 10 10 100.00
sec_cm_esc_rx_clk_bkgn_chk 10 10 100.00
pwrmgr_esc_clk_rst_malfunc 1.000s 31.287us 10 10 100.00
sec_cm_esc_rx_clk_local_esc 5 5 100.00
pwrmgr_sec_cm 3.140s 674.940us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
pwrmgr_sec_cm 3.140s 674.940us 5 5 100.00
sec_cm_fsm_terminal 5 5 100.00
pwrmgr_sec_cm 3.140s 674.940us 5 5 100.00
sec_cm_ctrl_flow_global_esc 10 10 100.00
pwrmgr_global_esc 1.060s 45.963us 10 10 100.00
sec_cm_main_pd_rst_local_esc 10 10 100.00
pwrmgr_glitch 1.080s 48.702us 10 10 100.00
sec_cm_ctrl_config_regwen 10 10 100.00
pwrmgr_sec_cm_ctrl_config_regwen 1.510s 473.975us 10 10 100.00
sec_cm_wakeup_config_regwen 5 5 100.00
pwrmgr_csr_rw 1.030s 49.878us 5 5 100.00
sec_cm_reset_config_regwen 5 5 100.00
pwrmgr_csr_rw 1.030s 49.878us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 6 10 60.00
pwrmgr_escalation_timeout 1.370s 100.116us 6 10 60.00
stress_all_with_rand_reset 8 10 80.00
pwrmgr_stress_all_with_rand_reset 13.540s 9079.637us 8 10 80.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 4 test runs
pwrmgr_reset 46127574130139989858120324409369423542145353068019521710286898334170039040681 116
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_reset 36098295170137831688906738448836316082302654894474672086906294910414553983102 104
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 33286900490375195719045688727741281044417287433872724716377499580472523607814 90
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 50142334758205656981746248866640226827145557648647316078778034646690648625517 83
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!clk_en) || status)' 4 test runs
pwrmgr_escalation_timeout 51564099529326181096130855761108487699668086953595077481597520144128628392720 79
UVM_ERROR @ 100115732 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 100115732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 91156406971060856189923533641843445418476803133337678781375156203769929898614 79
UVM_ERROR @ 99239819 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 99239819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 23128499376561267212920914692806967552544510777797189000964507551950274351953 79
UVM_ERROR @ 97236897 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 97236897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 95016522710042617111754558440527912604746399463296045117087124296666453914617 79
UVM_ERROR @ 387940932 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 387940932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 2 test runs
pwrmgr_stress_all_with_rand_reset 102503670249819740994165723245723596265028081294313540182479611521918636385161 1801
UVM_INFO @ 25637406081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_stress_all 107030597105079665695483815340707708380299987269268363477800952351936326470893 158
UVM_INFO @ 10063923407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [pwrmgr_common_vseq] wait timeout occurred! 1 test run
pwrmgr_stress_all_with_rand_reset 100481491866734045289143704320830470060528908594832616578225004996731285458218 1286
UVM_INFO @ 10933346454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitOtpInit 1 test run
pwrmgr_reset_invalid 114966891808349206352611960487619932069370160719463244830573714612742518765225 106
UVM_INFO @ 69884658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitResetPrep 1 test run
pwrmgr_reset_invalid 30626043615811846649866036431141803312733952489259790286088837476734379581702 88
UVM_INFO @ 41645214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitStrap 1 test run
pwrmgr_reset_invalid 37094990463351981799764411252658274536933625509243879778894178502916494580461 121
UVM_INFO @ 109302524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---