Simulation Results: rom_ctrl/32kb

 
30/05/2026 15:09:44 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.80 %
  • code
  • 99.68 %
  • assert
  • 97.67 %
  • func
  • 99.05 %
  • line
  • 99.59 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
96.61%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 6.220s 180.630us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 6.540s 333.487us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 6.980s 167.164us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.640s 164.237us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.760s 209.565us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.340s 172.871us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 6.980s 167.164us 5 5 100.00
rom_ctrl_csr_aliasing 3.760s 209.565us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 8.670s 1813.449us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.510s 126.903us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 7.100s 226.021us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 31.500s 595.906us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 8.660s 298.357us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 6.310s 1418.469us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 12.040s 551.427us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 12.040s 551.427us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 6.540s 333.487us 1 1 100.00
rom_ctrl_csr_rw 6.980s 167.164us 5 5 100.00
rom_ctrl_csr_aliasing 3.760s 209.565us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.420s 2016.716us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 6.540s 333.487us 1 1 100.00
rom_ctrl_csr_rw 6.980s 167.164us 5 5 100.00
rom_ctrl_csr_aliasing 3.760s 209.565us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.420s 2016.716us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 123.670s 1897.983us 18 20 90.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 32.960s 1546.449us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 239.260s 670.291us 5 5 100.00
rom_ctrl_tl_intg_err 82.890s 2809.555us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 239.260s 670.291us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 239.260s 670.291us 5 5 100.00
sec_cm_checker_ctr_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 123.670s 1897.983us 18 20 90.00
sec_cm_checker_ctrl_flow_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 123.670s 1897.983us 18 20 90.00
sec_cm_checker_fsm_local_esc 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 123.670s 1897.983us 18 20 90.00
sec_cm_compare_ctrl_flow_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 123.670s 1897.983us 18 20 90.00
sec_cm_compare_ctr_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 123.670s 1897.983us 18 20 90.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 239.260s 670.291us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 239.260s 670.291us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 6.220s 180.630us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 6.220s 180.630us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 6.220s 180.630us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 82.890s 2809.555us 25 25 100.00
sec_cm_bus_local_esc 20 22 90.91
rom_ctrl_corrupt_sig_fatal_chk 123.670s 1897.983us 18 20 90.00
rom_ctrl_kmac_err_chk 8.660s 298.357us 2 2 100.00
sec_cm_mux_mubi 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 123.670s 1897.983us 18 20 90.00
sec_cm_mux_consistency 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 123.670s 1897.983us 18 20 90.00
sec_cm_ctrl_redun 18 20 90.00
rom_ctrl_corrupt_sig_fatal_chk 123.670s 1897.983us 18 20 90.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 32.960s 1546.449us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 239.260s 670.291us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 18 20 90.00
rom_ctrl_stress_all_with_rand_reset 547.630s 23008.828us 18 20 90.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) 2 test runs
rom_ctrl_corrupt_sig_fatal_chk 44151355589310891092841379527602652351254967601805605821520824488731489853841 88
UVM_INFO @ 157091215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 14985401642062369166726108092557793970481961614599731146557872952999549739573 84
UVM_INFO @ 3673741466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [rom_ctrl_common_vseq] wait timeout occurred! 1 test run
rom_ctrl_stress_all_with_rand_reset 32928857420988511429964234653411954643496135431392208622601456833178187785907 143
UVM_INFO @ 25609999296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:235) [scoreboard] Check failed item.d_data[i**+:*] == exp_data[i**+:*] (* [*] vs * [*]) TLUL ROM read data incorrect 1 test run
rom_ctrl_stress_all_with_rand_reset 6214539959824565766295317663795407459371423076811749487451031601336234703917 167
UVM_INFO @ 21630963785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---