| V1 |
|
100.00% |
| V2 |
|
86.61% |
| V2S |
|
100.00% |
| V3 |
|
42.50% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 20 | 20 | 100.00 | |||
| rv_timer_random | 3.130s | 946.462us | 20 | 20 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.750s | 16.214us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| rv_timer_csr_rw | 0.950s | 12.119us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| rv_timer_csr_bit_bash | 3.210s | 488.970us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| rv_timer_csr_aliasing | 0.710s | 40.082us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 1.240s | 53.355us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| rv_timer_csr_rw | 0.950s | 12.119us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 0.710s | 40.082us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 3 | 20 | 15.00 | |||
| rv_timer_random_reset | 9.860s | 6292.352us | 3 | 20 | 15.00 | |
| disabled | 20 | 20 | 100.00 | |||
| rv_timer_disabled | 2.690s | 1144.274us | 20 | 20 | 100.00 | |
| cfg_update_on_fly | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 712.940s | 556849.830us | 10 | 10 | 100.00 | |
| no_interrupt_test | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 712.940s | 556849.830us | 10 | 10 | 100.00 | |
| stress | 20 | 20 | 100.00 | |||
| rv_timer_stress_all | 11.550s | 3873.956us | 20 | 20 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| rv_timer_alert_test | 0.920s | 37.960us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| rv_timer_intr_test | 1.010s | 34.050us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| rv_timer_tl_errors | 3.460s | 374.455us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| rv_timer_tl_errors | 3.460s | 374.455us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.750s | 16.214us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.950s | 12.119us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 0.710s | 40.082us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.130s | 299.971us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.750s | 16.214us | 1 | 1 | 100.00 | |
| rv_timer_csr_rw | 0.950s | 12.119us | 5 | 5 | 100.00 | |
| rv_timer_csr_aliasing | 0.710s | 40.082us | 1 | 1 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.130s | 299.971us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| rv_timer_sec_cm | 1.370s | 95.862us | 5 | 5 | 100.00 | |
| rv_timer_tl_intg_err | 1.960s | 231.499us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| rv_timer_tl_intg_err | 1.960s | 231.499us | 25 | 25 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 3 | 10 | 30.00 | |||
| rv_timer_min | 1.260s | 207.191us | 3 | 10 | 30.00 | |
| max_value | 0 | 10 | 0.00 | |||
| rv_timer_max | 1.840s | 323.592us | 0 | 10 | 0.00 | |
| stress_all_with_rand_reset | 14 | 20 | 70.00 | |||
| rv_timer_stress_all_with_rand_reset | 61.170s | 6548.025us | 14 | 20 | 70.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * | 24 test runs | |||
| rv_timer_min | 111431940513648690344664206377556279786376129487385018543592986215274191137866 | 75 |
UVM_INFO @ 98212227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 77077585149663064256480052092248434089839200818795525260792431029348284501257 | 75 |
UVM_INFO @ 207190646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 14317302283126148468167838075977845056390417953447231972881083382670692934675 | 75 |
UVM_INFO @ 78987906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 48125484805394159474116025592052095837658727399439590293400166221764485360593 | 75 |
UVM_INFO @ 886284107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 62501323315073843778220404773460296413446916943338548871573969328239952448697 | 76 |
UVM_INFO @ 6935832876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 104021104365819109015985141064058113865846001359987125261994451956680153227659 | 77 |
UVM_INFO @ 72435170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 58679948659043369067286638373618659875686414687417698618030610211399077285396 | 76 |
UVM_INFO @ 335226830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 81397639034447002361864028006996683336831247566125345176140192818118544268834 | 75 |
UVM_INFO @ 190290508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 104074647605841351135984412992450958327004447954171667325279251615481947005114 | 75 |
UVM_INFO @ 67075408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 90690235518825659307314668583367568422378028897940342058373744137656260311097 | 75 |
UVM_INFO @ 360805294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 9013574310537386510650743201476994468915391802056604614298745247185688260694 | 75 |
UVM_INFO @ 325260206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 53568001399647144451184284602156760806306162427556436498524548670032546056923 | 75 |
UVM_INFO @ 115588549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 82265417910043707477985923154240157074613414543769025511891733696246539921037 | 77 |
UVM_INFO @ 278621224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 114289057298179213974067007582885967488307391699678109956836754452244394182231 | 76 |
UVM_INFO @ 66471079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 84197106238227452119046881055842241020400905210776001769047555610993486170805 | 75 |
UVM_INFO @ 660520097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 104952516094159472109149930055603429222527889309465806963597936096269290123183 | 76 |
UVM_INFO @ 9415039751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 33127199809376804675683767849618827270737092101081225060881408900489523653960 | 75 |
UVM_INFO @ 1698172337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 97238391115002774682005665643757631976849505858035789859888962833787372388554 | 75 |
UVM_INFO @ 4953733447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 41280326674427347457334984055959028843628063747715277328850797343073494759582 | 75 |
UVM_INFO @ 218112943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 543110434334301805701214825676009255209648269901478858560505849767489701858 | 76 |
UVM_INFO @ 585369834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 49355995184094155397076409341936105714981152601587168455725252964119153618509 | 75 |
UVM_INFO @ 252232918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 29807726600019199945536853885189899264436240833882442396026861954665949054374 | 75 |
UVM_INFO @ 261805577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 44005379884003967451037900794313325495220517851802380907960749297141996294735 | 76 |
UVM_INFO @ 138816879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 4234103821899419058154680922836768547550641493691434490415959771798251889491 | 78 |
UVM_INFO @ 6292351820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | 8 test runs | |||
| rv_timer_max | 17978841580604340268833038393588698229847198525020574338726772166924318592448 | 75 |
UVM_INFO @ 690559394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 43362119975945392745025200661431656775070374502390637424938177642844743107495 | 75 |
UVM_INFO @ 45995432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 47374438709562142028767637789441373165481085279221236763044677247184248393057 | 75 |
UVM_INFO @ 161150696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 6072604186449778579734650438774726446730084101331248527062135182746182723061 | 75 |
UVM_INFO @ 44133291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 47726571424084717059055927029254295291526618657237563998808910982688210315087 | 75 |
UVM_INFO @ 44735702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 21522759387870334370608934676875831308729900982582046127656398569763945091117 | 76 |
UVM_INFO @ 51254947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 108641113935739425707320662428541143285945984002677663361749992807586500187561 | 75 |
UVM_INFO @ 89165950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 100149126914760312799645661167418996367474938359875751199857735910880532217906 | 75 |
UVM_INFO @ 220847800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) | 3 test runs | |||
| rv_timer_stress_all_with_rand_reset | 23220026067594141578572347303234602561071735453689971579065388806381654068497 | 112 |
UVM_INFO @ 397510808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 41996018742068440510094285420184042376183801539258688144434199825573744412148 | 186 |
UVM_INFO @ 4396406678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 61098142705822157145362110327189478841941097908091344223913221530711736643167 | 105 |
UVM_INFO @ 3156025027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | 3 test runs | |||
| rv_timer_stress_all_with_rand_reset | 23190207629835104508633727436593004866634752294917899849758064803706712517675 | 325 |
UVM_INFO @ 4812281927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 114395152301959275952209105367783174482059268408693107726672287165648347303757 | 117 |
UVM_INFO @ 198618183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 7145955513397788003627169752762285124351088604127350590312993155631842860261 | 209 |
UVM_INFO @ 8872047735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:346) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) | 2 test runs | |||
| rv_timer_max | 89997983352241477583317386192465304010732258326614209500833857629558325379686 | 75 |
UVM_INFO @ 323592446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 58390759728943940383535822340459641046750706780167569641020904574835154247445 | 75 |
UVM_INFO @ 178984950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|