| V1 |
|
100.00% |
| V2 |
|
99.74% |
| V2S |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 25 | 25 | 100.00 | |||
| spi_device_flash_and_tpm | 457.760s | 818242.773us | 25 | 25 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| spi_device_csr_hw_reset | 1.350s | 38.945us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| spi_device_csr_rw | 2.250s | 291.418us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| spi_device_csr_bit_bash | 9.790s | 844.567us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| spi_device_csr_aliasing | 14.140s | 3280.034us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| spi_device_csr_mem_rw_with_rand_reset | 4.650s | 535.956us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| spi_device_csr_rw | 2.250s | 291.418us | 5 | 5 | 100.00 | |
| spi_device_csr_aliasing | 14.140s | 3280.034us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| spi_device_mem_walk | 0.770s | 45.243us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| spi_device_mem_partial_access | 1.410s | 127.557us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| csb_read | 15 | 15 | 100.00 | |||
| spi_device_csb_read | 1.210s | 52.663us | 15 | 15 | 100.00 | |
| mem_parity | 20 | 20 | 100.00 | |||
| spi_device_mem_parity | 1.540s | 114.227us | 20 | 20 | 100.00 | |
| mem_cfg | 1 | 1 | 100.00 | |||
| spi_device_ram_cfg | 1.150s | 74.360us | 1 | 1 | 100.00 | |
| tpm_read | 15 | 15 | 100.00 | |||
| spi_device_tpm_rw | 10.800s | 454.620us | 15 | 15 | 100.00 | |
| tpm_write | 15 | 15 | 100.00 | |||
| spi_device_tpm_rw | 10.800s | 454.620us | 15 | 15 | 100.00 | |
| tpm_hw_reg | 30 | 30 | 100.00 | |||
| spi_device_tpm_read_hw_reg | 25.690s | 46701.878us | 15 | 15 | 100.00 | |
| spi_device_tpm_sts_read | 1.500s | 102.430us | 15 | 15 | 100.00 | |
| tpm_fully_random_case | 15 | 15 | 100.00 | |||
| spi_device_tpm_all | 32.500s | 30290.043us | 15 | 15 | 100.00 | |
| pass_cmd_filtering | 39 | 40 | 97.50 | |||
| spi_device_pass_cmd_filtering | 21.540s | 10054.439us | 15 | 15 | 100.00 | |
| spi_device_flash_all | 438.350s | 202866.220us | 24 | 25 | 96.00 | |
| pass_addr_translation | 39 | 40 | 97.50 | |||
| spi_device_pass_addr_payload_swap | 23.040s | 33403.128us | 15 | 15 | 100.00 | |
| spi_device_flash_all | 438.350s | 202866.220us | 24 | 25 | 96.00 | |
| pass_payload_translation | 39 | 40 | 97.50 | |||
| spi_device_pass_addr_payload_swap | 23.040s | 33403.128us | 15 | 15 | 100.00 | |
| spi_device_flash_all | 438.350s | 202866.220us | 24 | 25 | 96.00 | |
| cmd_info_slots | 24 | 25 | 96.00 | |||
| spi_device_flash_all | 438.350s | 202866.220us | 24 | 25 | 96.00 | |
| cmd_read_status | 39 | 40 | 97.50 | |||
| spi_device_intercept | 12.810s | 21923.829us | 15 | 15 | 100.00 | |
| spi_device_flash_all | 438.350s | 202866.220us | 24 | 25 | 96.00 | |
| cmd_read_jedec | 39 | 40 | 97.50 | |||
| spi_device_intercept | 12.810s | 21923.829us | 15 | 15 | 100.00 | |
| spi_device_flash_all | 438.350s | 202866.220us | 24 | 25 | 96.00 | |
| cmd_read_sfdp | 39 | 40 | 97.50 | |||
| spi_device_intercept | 12.810s | 21923.829us | 15 | 15 | 100.00 | |
| spi_device_flash_all | 438.350s | 202866.220us | 24 | 25 | 96.00 | |
| cmd_fast_read | 39 | 40 | 97.50 | |||
| spi_device_intercept | 12.810s | 21923.829us | 15 | 15 | 100.00 | |
| spi_device_flash_all | 438.350s | 202866.220us | 24 | 25 | 96.00 | |
| cmd_read_pipeline | 39 | 40 | 97.50 | |||
| spi_device_intercept | 12.810s | 21923.829us | 15 | 15 | 100.00 | |
| spi_device_flash_all | 438.350s | 202866.220us | 24 | 25 | 96.00 | |
| flash_cmd_upload | 15 | 15 | 100.00 | |||
| spi_device_upload | 22.550s | 28259.221us | 15 | 15 | 100.00 | |
| mailbox_command | 15 | 15 | 100.00 | |||
| spi_device_mailbox | 63.860s | 9562.902us | 15 | 15 | 100.00 | |
| mailbox_cross_outside_command | 15 | 15 | 100.00 | |||
| spi_device_mailbox | 63.860s | 9562.902us | 15 | 15 | 100.00 | |
| mailbox_cross_inside_command | 15 | 15 | 100.00 | |||
| spi_device_mailbox | 63.860s | 9562.902us | 15 | 15 | 100.00 | |
| cmd_read_buffer | 30 | 30 | 100.00 | |||
| spi_device_flash_mode | 19.640s | 10007.332us | 15 | 15 | 100.00 | |
| spi_device_read_buffer_direct | 12.220s | 5210.650us | 15 | 15 | 100.00 | |
| cmd_dummy_cycle | 39 | 40 | 97.50 | |||
| spi_device_mailbox | 63.860s | 9562.902us | 15 | 15 | 100.00 | |
| spi_device_flash_all | 438.350s | 202866.220us | 24 | 25 | 96.00 | |
| quad_spi | 24 | 25 | 96.00 | |||
| spi_device_flash_all | 438.350s | 202866.220us | 24 | 25 | 96.00 | |
| dual_spi | 24 | 25 | 96.00 | |||
| spi_device_flash_all | 438.350s | 202866.220us | 24 | 25 | 96.00 | |
| 4b_3b_feature | 15 | 15 | 100.00 | |||
| spi_device_cfg_cmd | 25.740s | 21227.042us | 15 | 15 | 100.00 | |
| write_enable_disable | 15 | 15 | 100.00 | |||
| spi_device_cfg_cmd | 25.740s | 21227.042us | 15 | 15 | 100.00 | |
| flash_mode_ignore_cmds | 15 | 15 | 100.00 | |||
| spi_device_flash_mode_ignore_cmds | 373.510s | 239807.713us | 15 | 15 | 100.00 | |
| TPM_with_flash_or_passthrough_mode | 25 | 25 | 100.00 | |||
| spi_device_flash_and_tpm | 457.760s | 818242.773us | 25 | 25 | 100.00 | |
| tpm_and_flash_trans_with_min_inactive_time | 25 | 25 | 100.00 | |||
| spi_device_flash_and_tpm_min_idle | 315.160s | 196724.112us | 25 | 25 | 100.00 | |
| stress_all | 15 | 15 | 100.00 | |||
| spi_device_stress_all | 505.440s | 70910.748us | 15 | 15 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| spi_device_alert_test | 1.120s | 37.685us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| spi_device_intr_test | 1.170s | 45.182us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| spi_device_tl_errors | 5.760s | 1264.103us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| spi_device_tl_errors | 5.760s | 1264.103us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| spi_device_csr_hw_reset | 1.350s | 38.945us | 1 | 1 | 100.00 | |
| spi_device_csr_rw | 2.250s | 291.418us | 5 | 5 | 100.00 | |
| spi_device_csr_aliasing | 14.140s | 3280.034us | 1 | 1 | 100.00 | |
| spi_device_same_csr_outstanding | 4.760s | 210.706us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| spi_device_csr_hw_reset | 1.350s | 38.945us | 1 | 1 | 100.00 | |
| spi_device_csr_rw | 2.250s | 291.418us | 5 | 5 | 100.00 | |
| spi_device_csr_aliasing | 14.140s | 3280.034us | 1 | 1 | 100.00 | |
| spi_device_same_csr_outstanding | 4.760s | 210.706us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| spi_device_sec_cm | 2.240s | 793.613us | 5 | 5 | 100.00 | |
| spi_device_tl_intg_err | 25.670s | 6695.383us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| spi_device_tl_intg_err | 25.670s | 6695.383us | 25 | 25 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) CSR last_read_addr compare mismatch act * != exp * | 1 test run | |||
| spi_device_flash_all | 52627507229957250836959928888672203757614367297288033963087448497711446815569 | 100 |
UVM_INFO @ 14677386156 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 6/12
UVM_INFO @ 14677386156 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 7/12
tl_ul_fuzzy_flash_status_q[i] = 0x520b02
UVM_INFO @ 17770651156 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 7/12
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