Simulation Results: spi_host

 
30/05/2026 15:09:44 DVSim: v1.49.0 sha: 1bd5f9a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.13 %
  • code
  • 95.03 %
  • assert
  • 96.59 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.45%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 71.000s 1993.749us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 25.813us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 2.000s 19.355us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 145.458us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 33.656us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 147.393us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 2.000s 19.355us 5 5 100.00
spi_host_csr_aliasing 2.000s 33.656us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 16.487us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 27.118us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 2.000s 22.193us 10 10 100.00
error_event_intr 30 30 100.00
spi_host_overflow_underflow 4.000s 322.427us 10 10 100.00
spi_host_error_cmd 2.000s 22.350us 10 10 100.00
spi_host_event 880.000s 127996.225us 10 10 100.00
clock_rate 10 10 100.00
spi_host_speed 6.000s 421.153us 10 10 100.00
speed 10 10 100.00
spi_host_speed 6.000s 421.153us 10 10 100.00
chip_select_timing 10 10 100.00
spi_host_speed 6.000s 421.153us 10 10 100.00
upper_range_clkdiv 4 5 80.00
spi_host_upper_range_clkdiv 206.000s 8500.495us 4 5 80.00
sw_reset 10 10 100.00
spi_host_sw_reset 8.000s 202.459us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 2.000s 61.298us 10 10 100.00
cpol_cpha 10 10 100.00
spi_host_speed 6.000s 421.153us 10 10 100.00
full_cycle 10 10 100.00
spi_host_speed 6.000s 421.153us 10 10 100.00
duplex 10 10 100.00
spi_host_smoke 71.000s 1993.749us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 71.000s 1993.749us 10 10 100.00
stress_all 10 10 100.00
spi_host_stress_all 68.000s 9006.542us 10 10 100.00
spien 10 10 100.00
spi_host_spien 35.000s 6239.545us 10 10 100.00
stall 10 10 100.00
spi_host_status_stall 239.000s 22015.076us 10 10 100.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 4.000s 574.379us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 4.000s 322.427us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 2.000s 34.297us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 2.000s 16.026us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 4.000s 353.084us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 4.000s 353.084us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 2.000s 25.813us 1 1 100.00
spi_host_csr_rw 2.000s 19.355us 5 5 100.00
spi_host_csr_aliasing 2.000s 33.656us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 40.183us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 2.000s 25.813us 1 1 100.00
spi_host_csr_rw 2.000s 19.355us 5 5 100.00
spi_host_csr_aliasing 2.000s 33.656us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 40.183us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 3.000s 333.700us 25 25 100.00
spi_host_sec_cm 2.000s 40.121us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 3.000s 333.700us 25 25 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
spi_host_upper_range_clkdiv 41855874561704804123686883940515584885631204613805166791713681589225112046653 127
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---