Simulation Results

Simulation Results: adc_ctrl

06/06/2026 15:22:54 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
67.34 %

code
95.61 %

assert
92.71 %

func
13.71 %

line
98.86 %

branch
97.40 %

cond
87.43 %

toggle
99.76 %

FSM
94.59 %

Validation stages

V1		100.00%
V2		49.72%
V2S		100.00%
V3		10.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	adc_ctrl_smoke	18.400s	5924.986us	10	10	100.00
csr_hw_reset				1	1	100.00
	adc_ctrl_csr_hw_reset	2.930s	1324.470us	1	1	100.00
csr_rw				5	5	100.00
	adc_ctrl_csr_rw	1.710s	538.931us	5	5	100.00
csr_bit_bash				1	1	100.00
	adc_ctrl_csr_bit_bash	69.390s	32806.251us	1	1	100.00
csr_aliasing				1	1	100.00
	adc_ctrl_csr_aliasing	3.520s	769.743us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	adc_ctrl_csr_mem_rw_with_rand_reset	2.330s	489.757us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	adc_ctrl_csr_rw	1.710s	538.931us	5	5	100.00
	adc_ctrl_csr_aliasing	3.520s	769.743us	1	1	100.00

88/177 passed

49.72 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
filters_polled				0	10	0.00
	adc_ctrl_filters_polled	2.430s	525.773us	0	10	0.00
filters_polled_fixed				0	10	0.00
	adc_ctrl_filters_polled_fixed	2.260s	431.071us	0	10	0.00
filters_interrupt				0	10	0.00
	adc_ctrl_filters_interrupt	2.140s	426.742us	0	10	0.00
filters_interrupt_fixed				0	10	0.00
	adc_ctrl_filters_interrupt_fixed	2.280s	463.040us	0	10	0.00
filters_wakeup				0	10	0.00
	adc_ctrl_filters_wakeup	2.220s	455.190us	0	10	0.00
filters_wakeup_fixed				0	10	0.00
	adc_ctrl_filters_wakeup_fixed	1.700s	412.451us	0	10	0.00
filters_both				0	10	0.00
	adc_ctrl_filters_both	2.080s	472.298us	0	10	0.00
clock_gating				0	10	0.00
	adc_ctrl_clock_gating	2.270s	417.249us	0	10	0.00
poweron_counter				10	10	100.00
	adc_ctrl_poweron_counter	15.970s	5396.692us	10	10	100.00
lowpower_counter				10	10	100.00
	adc_ctrl_lowpower_counter	99.940s	45046.159us	10	10	100.00
fsm_reset				10	10	100.00
	adc_ctrl_fsm_reset	265.170s	121801.439us	10	10	100.00
stress_all				1	10	10.00
	adc_ctrl_stress_all	112.610s	96268.256us	1	10	10.00
alert_test				10	10	100.00
	adc_ctrl_alert_test	2.440s	511.389us	10	10	100.00
intr_test				10	10	100.00
	adc_ctrl_intr_test	2.290s	407.945us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	adc_ctrl_tl_errors	3.970s	366.080us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	adc_ctrl_tl_errors	3.970s	366.080us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	adc_ctrl_csr_hw_reset	2.930s	1324.470us	1	1	100.00
	adc_ctrl_csr_rw	1.710s	538.931us	5	5	100.00
	adc_ctrl_csr_aliasing	3.520s	769.743us	1	1	100.00
	adc_ctrl_same_csr_outstanding	7.210s	2498.989us	5	5	100.00
tl_d_partial_access				12	12	100.00
	adc_ctrl_csr_hw_reset	2.930s	1324.470us	1	1	100.00
	adc_ctrl_csr_rw	1.710s	538.931us	5	5	100.00
	adc_ctrl_csr_aliasing	3.520s	769.743us	1	1	100.00
	adc_ctrl_same_csr_outstanding	7.210s	2498.989us	5	5	100.00

V2S

30/30 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	adc_ctrl_sec_cm	7.050s	8381.341us	5	5	100.00
	adc_ctrl_tl_intg_err	20.840s	8689.668us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	adc_ctrl_tl_intg_err	20.840s	8689.668us	25	25	100.00

1/10 passed

10.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	10	10.00
	adc_ctrl_stress_all_with_rand_reset	6.740s	1258.438us	1	10	10.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [, ]				98 test runs
	adc_ctrl_filters_polled	102426727854638772073400704662868567185867655572580060459792349970019075706563	386	UVM_INFO @ 276171386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	49610475978781993674809607387544522575062799939972957698502997995058424722211	386	UVM_INFO @ 291525226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	5400448361629461309852471285405469754400702296984159686883982227084844159649	386	UVM_INFO @ 417328679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	2640312146157189288236669067162490905648223571912754515863075791630861308858	386	UVM_INFO @ 331710213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	8577224732270352150824552783180370637642419477901059925430344360471081505660	386	UVM_INFO @ 455190382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	64523103321929965502011998134154569979172610828534252457936875835198048478219	386	UVM_INFO @ 333589163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	61093406618218576982567699687230913462539594819965644180636341734675111253668	386	UVM_INFO @ 477806978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	103562422520153349358717522934079334911020873218986032895228358678596350055647	386	UVM_INFO @ 372798553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	63185703498020657935719116821105065638542009358668736403556657263200061555774	399	UVM_INFO @ 786618461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	91638069763827588556416769025714455640453990235702020085222518563103412852509	494	UVM_INFO @ 41550937182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	33830062101974353626410840839264095023424104105875872939690509291994330885873	386	UVM_INFO @ 385555715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	93666838221355559671674654447666127082721108577127156120756605893388170880160	386	UVM_INFO @ 433736074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	36293287978727820554866487413271886933833575377266892660936707711434580449758	386	UVM_INFO @ 348102310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	102616049457733492325045648467842474178890865517745929505106859466825157845921	386	UVM_INFO @ 474983148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	91190725942413334356051231337377560977485806213942164005690834580666847218125	386	UVM_INFO @ 377374521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	89070001598703440762258545396617378653084603280088478242707191691169095865627	386	UVM_INFO @ 486505388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	40134503911494002106575625990598137288573829155605258128510362109734929984948	386	UVM_INFO @ 277870997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	78547155342458037561592622581783646102495019716729494029134614061803848304524	386	UVM_INFO @ 352151687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	9975968733031882584726112292131941687568624184310113531075155476070076676815	392	UVM_INFO @ 920123316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	68583557003711468152360035146790074829321592436777904617717151278105158895981	387	UVM_INFO @ 858070843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	53135385000025444766130011403601982708816458316756741174271348590342544025266	386	UVM_INFO @ 356087896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	27183278699898815755141627977717432350354490239957676735062897990197994834957	386	UVM_INFO @ 307754807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	18857804179431355290044781897361581699427146763771203618742491113442540039241	386	UVM_INFO @ 323576096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	83249676161192788016173349723258024852276240455938989238389604762745882927848	386	UVM_INFO @ 438346490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	13872871626559296206070289980489498170413906643421508423763027137477277411131	386	UVM_INFO @ 388830866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	100852852786366909489999933111304384969045803014500522418158868950297280643278	386	UVM_INFO @ 409274142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	110592698650578717328437479019015950379602888052505646947570022735143949005927	386	UVM_INFO @ 361746089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	15716093947973315661970446328564995357109570063183211766501037659261583822360	386	UVM_INFO @ 374415895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	37157943424707955631641057199213623775045345753723298136696790572541110100811	406	UVM_INFO @ 993533104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	51429156529276714751943095349371901547088697047410998366582207935153562009168	387	UVM_INFO @ 875168081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	23294485554043515942560646698290765044830925117474300706443065739576312069401	386	UVM_INFO @ 525773096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	17027872906554359401301504031690455030689045809211141060052390634529594276756	386	UVM_INFO @ 422559635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	52122036576167310683633119543855897939154762634953337279406717508001777236900	386	UVM_INFO @ 436770371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	30176648999019416265013705508765340431307281425868055597848905180632951957917	386	UVM_INFO @ 299060241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	102944538808975767713885356418589738725209887607281102031521350723206484896479	386	UVM_INFO @ 293183534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	29351034048898228099750311631977952163497143993470247913890470547377511602768	386	UVM_INFO @ 380161139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	84965531921274230975120408159209325512044223020339684857252091571270980155330	386	UVM_INFO @ 434558249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	43347791677489951571724578133032357761173533814456297432261835116620895921431	386	UVM_INFO @ 460397969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	39282654483130746055404584302294981146576944373854066470549568810550043912082	406	UVM_INFO @ 717854632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	37469765556528713955835827859115660918690274438394540563912707098332469287742	387	UVM_INFO @ 809732689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	87197259076620236408305750430770265723284235479555246476521135987765015850156	386	UVM_INFO @ 424223880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	66271566146426038713951519714786512818005363966144638272079622848280721829154	386	UVM_INFO @ 280005347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	96232224414386899022437796835612737866770997858053147381318836130094859522672	386	UVM_INFO @ 462868789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	20749431868519066317308344911694087612728865095054044230423946343978784846454	386	UVM_INFO @ 396402914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	93917723240491090838090983357658456245287281547621504181660132764885752181137	386	UVM_INFO @ 522862445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	54644091107217919220560954300799420030424270352913898113630073377105248565410	386	UVM_INFO @ 432776367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	96795848626807149516629607882158179234726237389230908120829470370716512154092	386	UVM_INFO @ 276667155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	18362284789230180288537792569057764188157960914576563497185124640232050827382	386	UVM_INFO @ 414406980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	19681410411928559246095770207369004507246936375323397168807511166439264301326	399	UVM_INFO @ 985697187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	110300177668433629140143103687357651367094107794314182374426686847851238505899	386	UVM_INFO @ 490075991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	89358674203589404739190167398629796127314296245395329942401053426919596922976	386	UVM_INFO @ 448129530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	30095861916260039210253161215834757458498995277527612714172706979150429060908	386	UVM_INFO @ 507799743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	93258708548960853894365484262272720106065436157335005738468662396511506793863	386	UVM_INFO @ 463039555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	37287518592161407637696305399033078321915112259721343476358611057341492791869	386	UVM_INFO @ 403002610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	83822084408913894849060367478227099520029658036263963924153729039293607681258	386	UVM_INFO @ 412450580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	26578641687267188967677348556761873661010274219983976953847060280450868151167	386	UVM_INFO @ 466979353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	16364903886890485251402282649702267321732803714624879364807043335472431686983	386	UVM_INFO @ 400998540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	47333239463951824834472386177165039461659425770506329029744013184466717674154	405	UVM_INFO @ 2610206075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	353011074569134564529497002248417417832444404610003194136675632280012385133	399	UVM_INFO @ 4082923048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	106229802245188032435930286150661919102223667041849117612246035644990318422198	386	UVM_INFO @ 513238989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	77810164227451586739015030372429083987509695416302126692775569672425259590499	386	UVM_INFO @ 502160917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	72835202019890302549337116298362805680420341668337072977874057722533246200892	386	UVM_INFO @ 426742281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	64419161975034091861162976061560253120859888112156248992552502475841811941775	386	UVM_INFO @ 411557294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	14469397628680177705267525764938630888750735856258481399602957023601139948280	386	UVM_INFO @ 281301814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	4019165883104529273742381344318128615443283295105355389754075725995772797340	386	UVM_INFO @ 307697748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	33835123112670124443363528431262838824305971143853415520693227512329633691863	386	UVM_INFO @ 448468306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	92445676892967981220408718901468721157463448262370435028852105174418723930427	386	UVM_INFO @ 450254588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	102957522174267704671621337906352418751958117713067869649793596068229542905086	387	UVM_INFO @ 619814892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	110139850291818181082833708704823263492491653847203465207804565276840626385146	386	UVM_INFO @ 437508826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	21182165231147265355483463430541427228867247284313023206895865021972700419201	386	UVM_INFO @ 485213599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	89881177402605001383736908952992344579784102181860689396752504678904056028987	386	UVM_INFO @ 423247717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	85700501758794382405434797256515061443499208051508204240887601560438375808396	386	UVM_INFO @ 448284756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	2619778328248338119386761654454203895467671931384907385161464364746351233983	386	UVM_INFO @ 471866509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	110523077115342229984060689823555634512423004863671686706726204413132482975909	386	UVM_INFO @ 285867710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	15341047090257113801836464047127684917618097278177148155369811549869219153978	386	UVM_INFO @ 297714912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	51157631817685177998346846999324435498738262687812647147360757313892439444999	386	UVM_INFO @ 293299068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	38789675121297618151671175347772927860061448198677895748141718857035453473473	392	UVM_INFO @ 739018993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	72850596223864228907396112213254305358641604800394479056173139349801329902378	449	UVM_INFO @ 24555583506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	100222820511440269252114169260179215941583286587660893568170676379007112309106	386	UVM_INFO @ 370612916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	62054018850156513411068542544522697147833143673801175690185411173649651855931	386	UVM_INFO @ 431071429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	13793461754536823470761027860584070664408702149304472008126896489869249193040	386	UVM_INFO @ 523083647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	9058505234099337301942449068096414739058817814887818465862188665140641025848	386	UVM_INFO @ 362720984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	96941211769335280552747425285653944851173553762296342557731514861380423894703	386	UVM_INFO @ 390721117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	43280968355877574653394334819880026323837623303003339640229939620361954485039	386	UVM_INFO @ 345706893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	90356264587501556769698505433265725886857471525755176723096960412856733950349	386	UVM_INFO @ 313303408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	59996253357113488233517588825441279626158452947541890930537424250398133049707	386	UVM_INFO @ 482299760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	88292188916639775999990980019989182966572856010845253839341228534552503761971	424	UVM_INFO @ 2125629595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	101535603145589013057073111876773454198259738854623213907261973398083344536368	412	UVM_INFO @ 4391980169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled	28228787788597090589975582312826857243146673010011148294715877679037950029348	386	UVM_INFO @ 399821980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	27461965750576728566642921207783385473262742632702809257053402813225708182186	386	UVM_INFO @ 397216888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	34318847078923216298769950797666867525502276501774401457759549581026335924025	386	UVM_INFO @ 386791622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	89387222548586112955320454582461954983757250234315617062837850270513602015953	386	UVM_INFO @ 305314612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	1338543814165148576690471767999121604769247430922408302829446409666412866063	386	UVM_INFO @ 320172836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	58872528356100023672796721369398351495915636061310628870999382487438910743647	386	UVM_INFO @ 355399745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	22307361623910722038103049917231649439054749831512412841939691311875577720644	386	UVM_INFO @ 417248521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	98964929024602786826453885463659373244081828501524245635726705139940425773780	386	UVM_INFO @ 472298030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all_with_rand_reset	26627718725056062556160352712075858993988136791192442488118259666467790127951	392	UVM_INFO @ 722549622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	65292628634465574878128680210713367779423923664640382799173732286502312333381	414	UVM_INFO @ 96268255909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---