| V1 |
|
100.00% |
| V2 |
|
99.54% |
| V2S |
|
93.57% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| wake_up | 1 | 1 | 100.00 | |||
| aes_wake_up | 3.000s | 59.535us | 1 | 1 | 100.00 | |
| smoke | 10 | 10 | 100.00 | |||
| aes_smoke | 5.000s | 76.588us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| aes_csr_hw_reset | 2.000s | 81.717us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| aes_csr_rw | 2.000s | 151.466us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| aes_csr_bit_bash | 5.000s | 343.727us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| aes_csr_aliasing | 14.000s | 220.965us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| aes_csr_mem_rw_with_rand_reset | 3.000s | 90.405us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| aes_csr_rw | 2.000s | 151.466us | 5 | 5 | 100.00 | |
| aes_csr_aliasing | 14.000s | 220.965us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| algorithm | 70 | 70 | 100.00 | |||
| aes_smoke | 5.000s | 76.588us | 10 | 10 | 100.00 | |
| aes_config_error | 31.000s | 1553.164us | 50 | 50 | 100.00 | |
| aes_stress | 173.000s | 7871.826us | 10 | 10 | 100.00 | |
| key_length | 70 | 70 | 100.00 | |||
| aes_smoke | 5.000s | 76.588us | 10 | 10 | 100.00 | |
| aes_config_error | 31.000s | 1553.164us | 50 | 50 | 100.00 | |
| aes_stress | 173.000s | 7871.826us | 10 | 10 | 100.00 | |
| back2back | 35 | 35 | 100.00 | |||
| aes_stress | 173.000s | 7871.826us | 10 | 10 | 100.00 | |
| aes_b2b | 27.000s | 113.360us | 25 | 25 | 100.00 | |
| backpressure | 10 | 10 | 100.00 | |||
| aes_stress | 173.000s | 7871.826us | 10 | 10 | 100.00 | |
| multi_message | 95 | 95 | 100.00 | |||
| aes_smoke | 5.000s | 76.588us | 10 | 10 | 100.00 | |
| aes_config_error | 31.000s | 1553.164us | 50 | 50 | 100.00 | |
| aes_stress | 173.000s | 7871.826us | 10 | 10 | 100.00 | |
| aes_alert_reset | 27.000s | 84.197us | 25 | 25 | 100.00 | |
| failure_test | 85 | 85 | 100.00 | |||
| aes_man_cfg_err | 3.000s | 61.699us | 10 | 10 | 100.00 | |
| aes_config_error | 31.000s | 1553.164us | 50 | 50 | 100.00 | |
| aes_alert_reset | 27.000s | 84.197us | 25 | 25 | 100.00 | |
| trigger_clear_test | 10 | 10 | 100.00 | |||
| aes_clear | 27.000s | 98.348us | 10 | 10 | 100.00 | |
| nist_test_vectors | 1 | 1 | 100.00 | |||
| aes_nist_vectors | 13.000s | 239.228us | 1 | 1 | 100.00 | |
| reset_recovery | 25 | 25 | 100.00 | |||
| aes_alert_reset | 27.000s | 84.197us | 25 | 25 | 100.00 | |
| stress | 10 | 10 | 100.00 | |||
| aes_stress | 173.000s | 7871.826us | 10 | 10 | 100.00 | |
| sideload | 20 | 20 | 100.00 | |||
| aes_stress | 173.000s | 7871.826us | 10 | 10 | 100.00 | |
| aes_sideload | 7.000s | 462.134us | 10 | 10 | 100.00 | |
| deinitialization | 10 | 10 | 100.00 | |||
| aes_deinit | 6.000s | 168.819us | 10 | 10 | 100.00 | |
| stress_all | 9 | 10 | 90.00 | |||
| aes_stress_all | 139.000s | 12894.168us | 9 | 10 | 90.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| aes_alert_test | 28.000s | 56.031us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| aes_tl_errors | 4.000s | 358.115us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| aes_tl_errors | 4.000s | 358.115us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| aes_csr_hw_reset | 2.000s | 81.717us | 1 | 1 | 100.00 | |
| aes_csr_rw | 2.000s | 151.466us | 5 | 5 | 100.00 | |
| aes_csr_aliasing | 14.000s | 220.965us | 1 | 1 | 100.00 | |
| aes_same_csr_outstanding | 3.000s | 161.763us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| aes_csr_hw_reset | 2.000s | 81.717us | 1 | 1 | 100.00 | |
| aes_csr_rw | 2.000s | 151.466us | 5 | 5 | 100.00 | |
| aes_csr_aliasing | 14.000s | 220.965us | 1 | 1 | 100.00 | |
| aes_same_csr_outstanding | 3.000s | 161.763us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| reseeding | 10 | 10 | 100.00 | |||
| aes_reseed | 8.000s | 378.681us | 10 | 10 | 100.00 | |
| fault_inject | 603 | 660 | 91.36 | |||
| aes_fi | 27.000s | 1963.942us | 10 | 10 | 100.00 | |
| aes_control_fi | 61.000s | 0.000us | 276 | 300 | 92.00 | |
| aes_cipher_fi | 61.000s | 0.000us | 317 | 350 | 90.57 | |
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors | 4.000s | 586.612us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors | 4.000s | 586.612us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors | 4.000s | 586.612us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors | 4.000s | 586.612us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors_with_csr_rw | 5.000s | 812.556us | 20 | 20 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| aes_sec_cm | 25.000s | 3727.630us | 5 | 5 | 100.00 | |
| aes_tl_intg_err | 5.000s | 972.624us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| aes_tl_intg_err | 5.000s | 972.624us | 25 | 25 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 25 | 25 | 100.00 | |||
| aes_alert_reset | 27.000s | 84.197us | 25 | 25 | 100.00 | |
| sec_cm_main_config_shadow | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors | 4.000s | 586.612us | 20 | 20 | 100.00 | |
| sec_cm_gcm_config_shadow | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors | 4.000s | 586.612us | 20 | 20 | 100.00 | |
| sec_cm_main_config_sparse | 139 | 145 | 95.86 | |||
| aes_smoke | 5.000s | 76.588us | 10 | 10 | 100.00 | |
| aes_stress | 173.000s | 7871.826us | 10 | 10 | 100.00 | |
| aes_alert_reset | 27.000s | 84.197us | 25 | 25 | 100.00 | |
| aes_core_fi | 63.000s | 10012.368us | 94 | 100 | 94.00 | |
| sec_cm_gcm_config_sparse | 154 | 160 | 96.25 | |||
| aes_config_error | 31.000s | 1553.164us | 50 | 50 | 100.00 | |
| aes_stress | 173.000s | 7871.826us | 10 | 10 | 100.00 | |
| aes_core_fi | 63.000s | 10012.368us | 94 | 100 | 94.00 | |
| sec_cm_aux_config_shadow | 20 | 20 | 100.00 | |||
| aes_shadow_reg_errors | 4.000s | 586.612us | 20 | 20 | 100.00 | |
| sec_cm_aux_config_regwen | 20 | 20 | 100.00 | |||
| aes_readability | 3.000s | 89.548us | 10 | 10 | 100.00 | |
| aes_stress | 173.000s | 7871.826us | 10 | 10 | 100.00 | |
| sec_cm_key_sideload | 20 | 20 | 100.00 | |||
| aes_stress | 173.000s | 7871.826us | 10 | 10 | 100.00 | |
| aes_sideload | 7.000s | 462.134us | 10 | 10 | 100.00 | |
| sec_cm_key_sw_unreadable | 10 | 10 | 100.00 | |||
| aes_readability | 3.000s | 89.548us | 10 | 10 | 100.00 | |
| sec_cm_data_reg_sw_unreadable | 10 | 10 | 100.00 | |||
| aes_readability | 3.000s | 89.548us | 10 | 10 | 100.00 | |
| sec_cm_key_sec_wipe | 10 | 10 | 100.00 | |||
| aes_readability | 3.000s | 89.548us | 10 | 10 | 100.00 | |
| sec_cm_iv_config_sec_wipe | 10 | 10 | 100.00 | |||
| aes_readability | 3.000s | 89.548us | 10 | 10 | 100.00 | |
| sec_cm_data_reg_sec_wipe | 10 | 10 | 100.00 | |||
| aes_readability | 3.000s | 89.548us | 10 | 10 | 100.00 | |
| sec_cm_data_reg_key_sca | 10 | 10 | 100.00 | |||
| aes_stress | 173.000s | 7871.826us | 10 | 10 | 100.00 | |
| sec_cm_key_masking | 10 | 10 | 100.00 | |||
| aes_stress | 173.000s | 7871.826us | 10 | 10 | 100.00 | |
| sec_cm_main_fsm_sparse | 10 | 10 | 100.00 | |||
| aes_fi | 27.000s | 1963.942us | 10 | 10 | 100.00 | |
| sec_cm_main_fsm_redun | 628 | 685 | 91.68 | |||
| aes_fi | 27.000s | 1963.942us | 10 | 10 | 100.00 | |
| aes_control_fi | 61.000s | 0.000us | 276 | 300 | 92.00 | |
| aes_cipher_fi | 61.000s | 0.000us | 317 | 350 | 90.57 | |
| aes_ctr_fi | 28.000s | 71.516us | 25 | 25 | 100.00 | |
| sec_cm_cipher_fsm_sparse | 10 | 10 | 100.00 | |||
| aes_fi | 27.000s | 1963.942us | 10 | 10 | 100.00 | |
| sec_cm_cipher_fsm_redun | 603 | 660 | 91.36 | |||
| aes_fi | 27.000s | 1963.942us | 10 | 10 | 100.00 | |
| aes_control_fi | 61.000s | 0.000us | 276 | 300 | 92.00 | |
| aes_cipher_fi | 61.000s | 0.000us | 317 | 350 | 90.57 | |
| sec_cm_cipher_ctr_redun | 317 | 350 | 90.57 | |||
| aes_cipher_fi | 61.000s | 0.000us | 317 | 350 | 90.57 | |
| sec_cm_ctr_fsm_sparse | 10 | 10 | 100.00 | |||
| aes_fi | 27.000s | 1963.942us | 10 | 10 | 100.00 | |
| sec_cm_ctr_fsm_redun | 311 | 335 | 92.84 | |||
| aes_fi | 27.000s | 1963.942us | 10 | 10 | 100.00 | |
| aes_control_fi | 61.000s | 0.000us | 276 | 300 | 92.00 | |
| aes_ctr_fi | 28.000s | 71.516us | 25 | 25 | 100.00 | |
| sec_cm_ghash_fsm_sparse | 10 | 10 | 100.00 | |||
| aes_fi | 27.000s | 1963.942us | 10 | 10 | 100.00 | |
| sec_cm_ctrl_sparse | 628 | 685 | 91.68 | |||
| aes_fi | 27.000s | 1963.942us | 10 | 10 | 100.00 | |
| aes_control_fi | 61.000s | 0.000us | 276 | 300 | 92.00 | |
| aes_cipher_fi | 61.000s | 0.000us | 317 | 350 | 90.57 | |
| aes_ctr_fi | 28.000s | 71.516us | 25 | 25 | 100.00 | |
| sec_cm_main_fsm_global_esc | 25 | 25 | 100.00 | |||
| aes_alert_reset | 27.000s | 84.197us | 25 | 25 | 100.00 | |
| sec_cm_main_fsm_local_esc | 628 | 685 | 91.68 | |||
| aes_fi | 27.000s | 1963.942us | 10 | 10 | 100.00 | |
| aes_control_fi | 61.000s | 0.000us | 276 | 300 | 92.00 | |
| aes_cipher_fi | 61.000s | 0.000us | 317 | 350 | 90.57 | |
| aes_ctr_fi | 28.000s | 71.516us | 25 | 25 | 100.00 | |
| sec_cm_cipher_fsm_local_esc | 628 | 685 | 91.68 | |||
| aes_fi | 27.000s | 1963.942us | 10 | 10 | 100.00 | |
| aes_control_fi | 61.000s | 0.000us | 276 | 300 | 92.00 | |
| aes_cipher_fi | 61.000s | 0.000us | 317 | 350 | 90.57 | |
| aes_ctr_fi | 28.000s | 71.516us | 25 | 25 | 100.00 | |
| sec_cm_ctr_fsm_local_esc | 311 | 335 | 92.84 | |||
| aes_fi | 27.000s | 1963.942us | 10 | 10 | 100.00 | |
| aes_control_fi | 61.000s | 0.000us | 276 | 300 | 92.00 | |
| aes_ctr_fi | 28.000s | 71.516us | 25 | 25 | 100.00 | |
| sec_cm_ghash_fsm_local_esc | 10 | 10 | 100.00 | |||
| aes_fi | 27.000s | 1963.942us | 10 | 10 | 100.00 | |
| sec_cm_data_reg_local_esc | 603 | 660 | 91.36 | |||
| aes_fi | 27.000s | 1963.942us | 10 | 10 | 100.00 | |
| aes_control_fi | 61.000s | 0.000us | 276 | 300 | 92.00 | |
| aes_cipher_fi | 61.000s | 0.000us | 317 | 350 | 90.57 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 10 | 0.00 | |||
| aes_stress_all_with_rand_reset | 52.000s | 1057.005us | 0 | 10 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! | 27 test runs | |||
| aes_cipher_fi | 94716633792664262001244553570322874682511491739374176346298195631352280085112 | 149 |
UVM_INFO @ 10017150377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 18350489643006883882558131524684667469087330948673619483656104715833430178861 | 144 |
UVM_INFO @ 10081370828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 109115890418383656467718474278225435764597956906128125880209968898649384063448 | 145 |
UVM_INFO @ 10004278426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 19778166037148922036409319942822090781061807694408780434604422190356461338620 | 143 |
UVM_INFO @ 10011535726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 20086275427264812973082653557083874883060810445213403056146115016633929665402 | 144 |
UVM_INFO @ 10028087584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 44535526031683754268760006546349785692213164639568598180943998189829037366763 | 142 |
UVM_INFO @ 10009128975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 79480622361685612767269938089238829985243634096309404827586382953553147447323 | 145 |
UVM_INFO @ 10036406244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 20503589851679304250383414792663117381939364452166150558991588330588688093467 | 144 |
UVM_INFO @ 10008445195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 25810113504027829098936873452386857209221412628544983798787330838861011290316 | 142 |
UVM_INFO @ 10081383144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 83469989393634795967366687755194231167336862324170172168555205744089686857536 | 143 |
UVM_INFO @ 10020343563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 86018694823264189317390679930666725785594623467782726319681301206218651833006 | 147 |
UVM_INFO @ 10023314163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 37118579253925719618637753984129597308327319188251078796833221893420445072552 | 145 |
UVM_INFO @ 10041835256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 11178683709920831720108551249425856230680765554514720014964021462729652538472 | 140 |
UVM_INFO @ 10007726653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 71697234909148664791257062993691735472970245102667656206653302143427855188220 | 140 |
UVM_INFO @ 10013488054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 110187239353673217015216935556468903793547459556136862668600646500758957404738 | 152 |
UVM_INFO @ 10021438872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 11817531843128993176775920863386639437646795809284838879510464592336891567334 | 139 |
UVM_INFO @ 10030042456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 65386345816240149507733971118331291162930759291846954023207322771037614778570 | 148 |
UVM_INFO @ 10010646847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 114955520386992500768147036609361179951815165926403521324339990469198019404539 | 143 |
UVM_INFO @ 10025604774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 22624144208401222251093743321942010277507096751405807358044441617828593231116 | 138 |
UVM_INFO @ 10021109825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 32443519940645533075417888727266182637652733275435546737607612554660231706493 | 147 |
UVM_INFO @ 10008519144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 14898414584225284723841282918494149749810405305892544069963348822669983708247 | 145 |
UVM_INFO @ 10107536434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 39571722806778920324147154288871821298126287855669570768765213774355596944904 | 142 |
UVM_INFO @ 10020433625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 66155456316867888600242703593018767955481896482990352263983347008413307242838 | 139 |
UVM_INFO @ 10008998841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 13713439189522123189239994475461172218693741899606163569600636301662751179852 | 154 |
UVM_INFO @ 10099163420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 71337796529692597477525731027575209429795703072708950076098644796248651261501 | 147 |
UVM_INFO @ 10015937702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 94111718273127436869645820922140844601119763300634697945560300844779386286471 | 140 |
UVM_INFO @ 10007397778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_cipher_fi | 90240330978056628633579710061583576460008852220827602761579286929833443845220 | 145 |
UVM_INFO @ 10038050095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | 16 test runs | |||
| aes_control_fi | 114501673401631717196758252934021018654311028701462680505275575839466555177030 | None | ||
| aes_control_fi | 99134308305494273760255059873877192558163854746115934907949548081135469318526 | None | ||
| aes_control_fi | 78423151955809777999797820117686293156083479507121062562546837848049129492553 | None | ||
| aes_cipher_fi | 111453853786928123494835508249965860181572971854026152921830987493560046384127 | None | ||
| aes_control_fi | 8084888417585955893423228081945683671076956784190932311570877527154754002103 | None | ||
| aes_control_fi | 87298352124376573930152629491255649470500081052351834195216356891586675306967 | None | ||
| aes_cipher_fi | 49096021035541572262970254452361338351830755639301845465416317656014798792982 | None | ||
| aes_control_fi | 28374721554199392980736264596723631853258151326945991795992452422909206614478 | None | ||
| aes_cipher_fi | 52324743459375187054015049609801525069987052526712663657187892238048881265525 | None | ||
| aes_control_fi | 64703732040654076688489117403362346930295337741166491849035929486083095972147 | None | ||
| aes_control_fi | 6454572631516587742104148748734949486530711985305079369348245813288457990718 | None | ||
| aes_control_fi | 820365005299457047242329746866934598223313586376893604600627247065666232239 | None | ||
| aes_cipher_fi | 61199655773940811563586890188202313336273591142447607662762721816046554042852 | None | ||
| aes_cipher_fi | 113153701883990886001450829511106482090054251238437917699047590229687940689420 | None | ||
| aes_control_fi | 39777531535204411354501528508029974338915863974291054104880932444923365392158 | None | ||
| aes_cipher_fi | 3961792222047492690424368751000062546936888839262778367243153309103483803553 | None | ||
| UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! | 14 test runs | |||
| aes_control_fi | 31537035381839565382743211184065726349889331628525774853148052349590902204126 | 142 |
UVM_INFO @ 10078603100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 71056616996066890797789164967630531820085527983072454368995656885962040161148 | 136 |
UVM_INFO @ 10006889083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 2964342952431276897829312915524740942893606429016533994526030204593491198558 | 144 |
UVM_INFO @ 10030927865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 31602703555274296234420146617949581301832208179811870186621221348028698325176 | 147 |
UVM_INFO @ 10041294609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 9013215192590339902722432258458379900924683287369167401361596224594472540851 | 146 |
UVM_INFO @ 10006870337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 108089599682285523735547129361386943401394567856375625377299352233718488376605 | 150 |
UVM_INFO @ 10073842865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 86456237740668724637642069759985257265253247861993621740305278131853730082347 | 149 |
UVM_INFO @ 10010222240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 113968966609462712769984997453773793749995180644932907244138028717308838442410 | 153 |
UVM_INFO @ 10013652728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 109002409834384037487091987104137945298478227634810391054968228566069505021327 | 150 |
UVM_INFO @ 10017214136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 53308582992890079033074191986680466677988704485930442223629017533193651397177 | 148 |
UVM_INFO @ 10026052909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 54645207161640753824555014210446834583176359331057477633132776395955206569196 | 150 |
UVM_INFO @ 10026862373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 6061550890332292720241322428796950486534954388328132408159071393276247072263 | 141 |
UVM_INFO @ 10008359316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 115646385980355654766642775599500346435481839097927061573814361418066034282377 | 141 |
UVM_INFO @ 10014243232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_control_fi | 17083518000115226883705126672200790907584010232197262468895046518292637217515 | 149 |
UVM_INFO @ 10005286050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) | 7 test runs | |||
| aes_stress_all_with_rand_reset | 50334575945192338799616269556431732043578881264787429022958393141037971415433 | 135 |
UVM_INFO @ 8523862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_stress_all_with_rand_reset | 86539438635818291992082623955525877775838268992883797798375715742488690759291 | 167 |
UVM_INFO @ 10339122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_stress_all_with_rand_reset | 74816065890622330232868960402402691714184358347501661694486408973898882693286 | 1666 |
UVM_INFO @ 1057005013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_stress_all_with_rand_reset | 97454553287071858089014390030946711668490255855889489780728537649116855650351 | 806 |
UVM_INFO @ 485900929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_stress_all_with_rand_reset | 88543133631939949857837800043813681859052951998847482047414987617515574051416 | 740 |
UVM_INFO @ 2670372053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_stress_all_with_rand_reset | 13216972346803390582253033788917991740329489056622625923242399310443752179079 | 213 |
UVM_INFO @ 1336338433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_stress_all_with_rand_reset | 56458378875990583011123919276156031382316122452255322146418061588024868388042 | 144 |
UVM_INFO @ 12783511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! | 5 test runs | |||
| aes_core_fi | 99451087615196686661200734515936451427732261790214553652437221525579568910121 | 149 |
UVM_INFO @ 10012367539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_core_fi | 53703508091529625781231251150333177613123679034253369364013039539674523437316 | 142 |
UVM_INFO @ 10010937172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_core_fi | 33348098875127326828726185906569264869453144685532870686307985044926368935081 | 148 |
UVM_INFO @ 10006343716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_core_fi | 99442269397288719189551987463333874182833038779665720986505226395192498044708 | 143 |
UVM_INFO @ 10007265442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| aes_core_fi | 29617554343648357883087446109544385317960199864422927165433802467660480591603 | 145 |
UVM_INFO @ 10090858733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:465) [aes_reseed_vseq] wait timeout occurred! | 1 test run | |||
| aes_stress_all | 52241633747041672723970010420821589490524195674271630841574346254959800312848 | 242502 |
UVM_INFO @ 12894168334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | 1 test run | |||
| aes_stress_all_with_rand_reset | 1367750706561545541104491181688409926849233704174301056381611736722241421940 | 473 |
UVM_INFO @ 10317251996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (aes_base_vseq.sv:1031) virtual_sequencer [aes_stress_vseq] | 1 test run | |||
| aes_stress_all_with_rand_reset | 87334138062057123750407286627226214709327694351952568132191142399968715826424 | 170 |
Was able to clear FATAL ALERT without reset
---| Idle: 0
---| Stall: 0
|
|
| UVM_FATAL (aes_base_vseq.sv:86) [aes_stress_all_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) | 1 test run | |||
| aes_stress_all_with_rand_reset | 12586990075731603980067722300813891275638996134168956484851372188089169036640 | 109 |
UVM_INFO @ 7701597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (aes_core_fi_vseq.sv:93) [aes_core_fi_vseq] wait timeout occurred! | 1 test run | |||
| aes_core_fi | 43267102229783180948127172034154844062160807561879789539230339196245032008556 | 138 |
UVM_INFO @ 10045108221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|