Simulation Results: aes/unmasked

 
06/06/2026 15:22:54 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.43 %
  • code
  • 93.11 %
  • assert
  • 98.11 %
  • func
  • 98.07 %
  • block
  • 94.13 %
  • line
  • 95.73 %
  • branch
  • 87.50 %
  • toggle
  • 98.08 %
  • FSM
  • 91.11 %
Validation stages
V1
100.00%
V2
99.54%
V2S
92.04%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 55.372us 1 1 100.00
smoke 10 10 100.00
aes_smoke 4.000s 159.102us 10 10 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 130.704us 1 1 100.00
csr_rw 5 5 100.00
aes_csr_rw 2.000s 58.217us 5 5 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 183.235us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 346.865us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 58.910us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
aes_csr_rw 2.000s 58.217us 5 5 100.00
aes_csr_aliasing 3.000s 346.865us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 70 70 100.00
aes_smoke 4.000s 159.102us 10 10 100.00
aes_config_error 6.000s 1279.136us 50 50 100.00
aes_stress 3.000s 83.335us 10 10 100.00
key_length 70 70 100.00
aes_smoke 4.000s 159.102us 10 10 100.00
aes_config_error 6.000s 1279.136us 50 50 100.00
aes_stress 3.000s 83.335us 10 10 100.00
back2back 35 35 100.00
aes_stress 3.000s 83.335us 10 10 100.00
aes_b2b 8.000s 397.765us 25 25 100.00
backpressure 10 10 100.00
aes_stress 3.000s 83.335us 10 10 100.00
multi_message 95 95 100.00
aes_smoke 4.000s 159.102us 10 10 100.00
aes_config_error 6.000s 1279.136us 50 50 100.00
aes_stress 3.000s 83.335us 10 10 100.00
aes_alert_reset 4.000s 83.320us 25 25 100.00
failure_test 85 85 100.00
aes_man_cfg_err 3.000s 57.779us 10 10 100.00
aes_config_error 6.000s 1279.136us 50 50 100.00
aes_alert_reset 4.000s 83.320us 25 25 100.00
trigger_clear_test 10 10 100.00
aes_clear 4.000s 214.203us 10 10 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 239.596us 1 1 100.00
reset_recovery 25 25 100.00
aes_alert_reset 4.000s 83.320us 25 25 100.00
stress 10 10 100.00
aes_stress 3.000s 83.335us 10 10 100.00
sideload 20 20 100.00
aes_stress 3.000s 83.335us 10 10 100.00
aes_sideload 5.000s 624.126us 10 10 100.00
deinitialization 10 10 100.00
aes_deinit 4.000s 430.968us 10 10 100.00
stress_all 9 10 90.00
aes_stress_all 20.000s 440.927us 9 10 90.00
alert_test 10 10 100.00
aes_alert_test 3.000s 53.865us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
aes_tl_errors 5.000s 1396.355us 25 25 100.00
tl_d_illegal_access 25 25 100.00
aes_tl_errors 5.000s 1396.355us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
aes_csr_hw_reset 2.000s 130.704us 1 1 100.00
aes_csr_rw 2.000s 58.217us 5 5 100.00
aes_csr_aliasing 3.000s 346.865us 1 1 100.00
aes_same_csr_outstanding 2.000s 92.552us 5 5 100.00
tl_d_partial_access 12 12 100.00
aes_csr_hw_reset 2.000s 130.704us 1 1 100.00
aes_csr_rw 2.000s 58.217us 5 5 100.00
aes_csr_aliasing 3.000s 346.865us 1 1 100.00
aes_same_csr_outstanding 2.000s 92.552us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 10 10 100.00
aes_reseed 4.000s 261.984us 10 10 100.00
fault_inject 595 660 90.15
aes_fi 4.000s 79.174us 10 10 100.00
aes_control_fi 61.000s 0.000us 266 300 88.67
aes_cipher_fi 61.000s 0.000us 319 350 91.14
shadow_reg_update_error 19 20 95.00
aes_shadow_reg_errors 3.000s 784.957us 19 20 95.00
shadow_reg_read_clear_staged_value 19 20 95.00
aes_shadow_reg_errors 3.000s 784.957us 19 20 95.00
shadow_reg_storage_error 19 20 95.00
aes_shadow_reg_errors 3.000s 784.957us 19 20 95.00
shadowed_reset_glitch 19 20 95.00
aes_shadow_reg_errors 3.000s 784.957us 19 20 95.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
aes_shadow_reg_errors_with_csr_rw 5.000s 287.639us 20 20 100.00
tl_intg_err 30 30 100.00
aes_sec_cm 6.000s 2874.827us 5 5 100.00
aes_tl_intg_err 3.000s 1072.308us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
aes_tl_intg_err 3.000s 1072.308us 25 25 100.00
sec_cm_lc_escalate_en_intersig_mubi 25 25 100.00
aes_alert_reset 4.000s 83.320us 25 25 100.00
sec_cm_main_config_shadow 19 20 95.00
aes_shadow_reg_errors 3.000s 784.957us 19 20 95.00
sec_cm_gcm_config_shadow 19 20 95.00
aes_shadow_reg_errors 3.000s 784.957us 19 20 95.00
sec_cm_main_config_sparse 133 145 91.72
aes_smoke 4.000s 159.102us 10 10 100.00
aes_stress 3.000s 83.335us 10 10 100.00
aes_alert_reset 4.000s 83.320us 25 25 100.00
aes_core_fi 157.000s 10022.228us 88 100 88.00
sec_cm_gcm_config_sparse 148 160 92.50
aes_config_error 6.000s 1279.136us 50 50 100.00
aes_stress 3.000s 83.335us 10 10 100.00
aes_core_fi 157.000s 10022.228us 88 100 88.00
sec_cm_aux_config_shadow 19 20 95.00
aes_shadow_reg_errors 3.000s 784.957us 19 20 95.00
sec_cm_aux_config_regwen 20 20 100.00
aes_readability 3.000s 211.558us 10 10 100.00
aes_stress 3.000s 83.335us 10 10 100.00
sec_cm_key_sideload 20 20 100.00
aes_stress 3.000s 83.335us 10 10 100.00
aes_sideload 5.000s 624.126us 10 10 100.00
sec_cm_key_sw_unreadable 10 10 100.00
aes_readability 3.000s 211.558us 10 10 100.00
sec_cm_data_reg_sw_unreadable 10 10 100.00
aes_readability 3.000s 211.558us 10 10 100.00
sec_cm_key_sec_wipe 10 10 100.00
aes_readability 3.000s 211.558us 10 10 100.00
sec_cm_iv_config_sec_wipe 10 10 100.00
aes_readability 3.000s 211.558us 10 10 100.00
sec_cm_data_reg_sec_wipe 10 10 100.00
aes_readability 3.000s 211.558us 10 10 100.00
sec_cm_data_reg_key_sca 10 10 100.00
aes_stress 3.000s 83.335us 10 10 100.00
sec_cm_key_masking 10 10 100.00
aes_stress 3.000s 83.335us 10 10 100.00
sec_cm_main_fsm_sparse 10 10 100.00
aes_fi 4.000s 79.174us 10 10 100.00
sec_cm_main_fsm_redun 620 685 90.51
aes_fi 4.000s 79.174us 10 10 100.00
aes_control_fi 61.000s 0.000us 266 300 88.67
aes_cipher_fi 61.000s 0.000us 319 350 91.14
aes_ctr_fi 3.000s 109.271us 25 25 100.00
sec_cm_cipher_fsm_sparse 10 10 100.00
aes_fi 4.000s 79.174us 10 10 100.00
sec_cm_cipher_fsm_redun 595 660 90.15
aes_fi 4.000s 79.174us 10 10 100.00
aes_control_fi 61.000s 0.000us 266 300 88.67
aes_cipher_fi 61.000s 0.000us 319 350 91.14
sec_cm_cipher_ctr_redun 319 350 91.14
aes_cipher_fi 61.000s 0.000us 319 350 91.14
sec_cm_ctr_fsm_sparse 10 10 100.00
aes_fi 4.000s 79.174us 10 10 100.00
sec_cm_ctr_fsm_redun 301 335 89.85
aes_fi 4.000s 79.174us 10 10 100.00
aes_control_fi 61.000s 0.000us 266 300 88.67
aes_ctr_fi 3.000s 109.271us 25 25 100.00
sec_cm_ghash_fsm_sparse 10 10 100.00
aes_fi 4.000s 79.174us 10 10 100.00
sec_cm_ctrl_sparse 620 685 90.51
aes_fi 4.000s 79.174us 10 10 100.00
aes_control_fi 61.000s 0.000us 266 300 88.67
aes_cipher_fi 61.000s 0.000us 319 350 91.14
aes_ctr_fi 3.000s 109.271us 25 25 100.00
sec_cm_main_fsm_global_esc 25 25 100.00
aes_alert_reset 4.000s 83.320us 25 25 100.00
sec_cm_main_fsm_local_esc 620 685 90.51
aes_fi 4.000s 79.174us 10 10 100.00
aes_control_fi 61.000s 0.000us 266 300 88.67
aes_cipher_fi 61.000s 0.000us 319 350 91.14
aes_ctr_fi 3.000s 109.271us 25 25 100.00
sec_cm_cipher_fsm_local_esc 620 685 90.51
aes_fi 4.000s 79.174us 10 10 100.00
aes_control_fi 61.000s 0.000us 266 300 88.67
aes_cipher_fi 61.000s 0.000us 319 350 91.14
aes_ctr_fi 3.000s 109.271us 25 25 100.00
sec_cm_ctr_fsm_local_esc 301 335 89.85
aes_fi 4.000s 79.174us 10 10 100.00
aes_control_fi 61.000s 0.000us 266 300 88.67
aes_ctr_fi 3.000s 109.271us 25 25 100.00
sec_cm_ghash_fsm_local_esc 10 10 100.00
aes_fi 4.000s 79.174us 10 10 100.00
sec_cm_data_reg_local_esc 595 660 90.15
aes_fi 4.000s 79.174us 10 10 100.00
aes_control_fi 61.000s 0.000us 266 300 88.67
aes_cipher_fi 61.000s 0.000us 319 350 91.14
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
aes_stress_all_with_rand_reset 17.000s 1295.964us 0 10 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 24 test runs
aes_control_fi 30491352441877863460651583693707440490900684761974041207562272277543515811700 143
UVM_INFO @ 10009728937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 15859300030834920621176968781067885208253770918624485872311490087714144914067 142
UVM_INFO @ 10014121555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 19795344155045596695262309976105400662615923801476800534360926271384237642164 153
UVM_INFO @ 10056674198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 15553429090515897965542198588158895442271234046520503762074463107140613534756 148
UVM_INFO @ 10013735257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 115525922187574273728691883448518494307346751783063499034797764813032301777900 143
UVM_INFO @ 10002182537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 86834551117141865637438919698740400021497726546551878195408040376878769422466 142
UVM_INFO @ 10015145226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 19490149195900506136454407894252638115488339545065333150357361574713357106446 147
UVM_INFO @ 10007776473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 12751227948100771337306812940785693762311801150756281961584720484250705057280 147
UVM_INFO @ 10011141088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 110838019234853884991361056974515047670623777370529617216421418249008535502953 148
UVM_INFO @ 10010201761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 89258295222681232028094666913992212863764453685362187211716447873092985739872 142
UVM_INFO @ 10011344678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 12956607661415553687329613519795127843931698753836103691021088840632353016135 148
UVM_INFO @ 10009637855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 90829076513796626672095199918062315252986183552696653650157298846540928161493 150
UVM_INFO @ 10015750794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 58532211793793024799634138312550445361231879672444433416089990927108984020378 138
UVM_INFO @ 10006318463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 97105570479722778875299785913043287907979356859154490921203812280611238102033 148
UVM_INFO @ 10006099241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 50491037746780648797156101091022352199326576680947975790928929863144902114286 143
UVM_INFO @ 10011212493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 47726290179155968161234825261917894983246197654815436162226503931877839018208 142
UVM_INFO @ 10019055353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 25428760278415601536643927409699631808422476000415726680444058099193060448659 139
UVM_INFO @ 10008530334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 112513400790651812048945590107350032701244853032620731413853448441612817892955 141
UVM_INFO @ 10053171962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 107624372791907862230550633300153227144301157865544700176797537708747038845148 146
UVM_INFO @ 10005818118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 33081897152132895480022804956088036642968733534020400029296092632942279140697 150
UVM_INFO @ 10007676482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 48268500509826069889751735104840747441245534762318353819735353943903452699819 150
UVM_INFO @ 10005489294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 39296374426274962445400128382631233317688072298090780716207790808595107523331 150
UVM_INFO @ 10004845311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 32214618832825401987416307734843000196188132027168159679064515567976708533077 147
UVM_INFO @ 10015759493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 74602606629356892310592579335592821443680722200979851209678480049411389457053 150
UVM_INFO @ 10044493626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 22 test runs
aes_cipher_fi 99762904054721816161422453082967433718014856555131817196066061204868351451520 None
aes_cipher_fi 1102434511461667535401024273341314230017969347033202939763067911156864081205 None
aes_cipher_fi 58499827096486674019474218276994576927850103865590494617769062472400675503097 None
aes_cipher_fi 62780071891659862893955278472118502461260542526207546618735335011021770196743 None
aes_control_fi 8381074488143066641332730307595469593585812988612776547646085973905549976600 None
aes_control_fi 32038080253808786756030513924123101809725858376999054784805872586991899905085 None
aes_cipher_fi 33150799678892206097609785254049140363903235138749347028343449774735133685625 None
aes_control_fi 42445788266970807650950970160630307286245883529840219456220210820402793981126 None
aes_cipher_fi 31922378478625092601156045372418559628760677275300934717634359533726987787646 None
aes_cipher_fi 20391177858861832376544853374580381036034898617859738304948669565412541589967 None
aes_control_fi 44393809374611809941526985117815317683692496145785237190043278441161880720975 None
aes_cipher_fi 49302303296583808724002416099551085004181045752945879399853091066545949597121 None
aes_control_fi 1610911084430653376888954941064906455381355452502793088411408827985106451873 None
aes_control_fi 90555929146400559381220503371418285062211316687079421928244344930600433763234 None
aes_cipher_fi 80483534797653171715984815516802348234668956586111283195546896164831152938475 None
aes_control_fi 72843646509578391846131570469329334037542676027999123508976173033045231866143 None
aes_control_fi 79109802479459689864809980390911634495710109057585562697636111407328688435703 None
aes_cipher_fi 34894364480792672300930496840718848606374519408083360257928199023486028271720 None
aes_control_fi 49625670063823110527957959620088338749995544983313329503955502282352097749730 None
aes_control_fi 109875236110687431753654807922453850994698756662992797465970665886207327861846 None
aes_cipher_fi 83377735234634046850186165809882748594519493670201659965612154323393464569569 None
aes_cipher_fi 78219653347353610632517240093214170150405353581503292560325659791096021504170 None
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 18 test runs
aes_cipher_fi 68228305542207613947232156749069562070023678350106047895546302033810235226373 145
UVM_INFO @ 10011606987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 94206872025730380032828493195270482307464821435070870728962856507292451007639 144
UVM_INFO @ 10011647753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 29416490520084949369558807665103697898222126664408307100198727430325520728022 143
UVM_INFO @ 10015049860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 14798229351195058153892983714908605912177788889269936560658462966145542672158 149
UVM_INFO @ 10009824781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 57107257365216333450203188258658061868696890122449029628175719063743356164480 137
UVM_INFO @ 10010357032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 74844763666772318429415373921067712130783429250581667395846209939014865212666 145
UVM_INFO @ 10012335489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 45073756317606136999502376878638684312664332162331643546967348894522589097373 148
UVM_INFO @ 10003224410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 44275890403176182117912284234788864866888442454481676111128267248665954553057 138
UVM_INFO @ 10005531599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 64087519042091345114624867564566204750233423209310085706729090043807871830947 152
UVM_INFO @ 10006415195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 111494526112681626525170273902074027801503212315219628863464356356098485849101 148
UVM_INFO @ 10015419759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 96953895836960019297305830152721936195515859629111654922299047211305195235352 150
UVM_INFO @ 10007823268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 13346397657575326589274431555919124267237281821983976726175300842917827659866 137
UVM_INFO @ 10005666040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 26024950312930415222144637514182939919058836585643493138784913391978720349292 145
UVM_INFO @ 10013406609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 57031703642454514641757797174970859899015261871487337960119105049397346528374 153
UVM_INFO @ 10014421840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 77286899740822887441269474566294346528165270268368066940201652490862914366012 155
UVM_INFO @ 10002583501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 92662464858607278463503924867852836778966419303754388423141133908709854185985 144
UVM_INFO @ 10015004992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 76419640289582207820828276774068956620088524496675430088951410463562596672389 148
UVM_INFO @ 10025877602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 97933866330757969640696773088052167379820877899239243176901910874852683127688 143
UVM_INFO @ 10005227690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 7 test runs
aes_stress_all_with_rand_reset 23263403731497319351710029249233571530422598985051938683760647870878941454737 1080
UVM_INFO @ 1755031423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 7943283323523298677932330746865226874500177345756676562440716286960774528659 527
UVM_INFO @ 2402252611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 110768279773469989996241770003978620559866973309208197223439259066207506511432 947
UVM_INFO @ 3370964430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 15664300931744086884192915108363590363054563281347332706432692905654699582777 194
UVM_INFO @ 8606315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 52603492043226241049939285110974790270891640510559867515732269916143605170353 232
UVM_INFO @ 545449921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 68467509026329191241696688111816021698651896235322475064614486891449424530876 167
UVM_INFO @ 10167828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 38677613833100047464780638257936829499889273272410955751981795679385623506298 1309
UVM_INFO @ 1295964181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 7 test runs
aes_core_fi 19910990402360732948528022712460314631950985641617170414437323237449840295640 145
UVM_INFO @ 10008652084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 30399452745276385947933602308248127511187370546766347875127640416777118419651 141
UVM_INFO @ 10025417425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 67552295153268439206297416523307900355120270988799710890306430199416746036392 141
UVM_INFO @ 10007021689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 70185044764924064784023573384255839707786999640595325728684186162443886033249 146
UVM_INFO @ 10013414730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 69883418747679745027116401989184538807772415594587336685252555990330639356418 150
UVM_INFO @ 10018731103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 15452705428027665665220883037814899454250296852116484409733222851205191109312 142
UVM_INFO @ 10037089784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 60944236519743504328550766153525034479177135471812681780210207111690452484076 152
UVM_INFO @ 10022422986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_stress_all_with_rand_reset 49647361962180653526642755409678900042619270280018094735159957399506117774742 430
UVM_INFO @ 1155736460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 1027979700003368178770835732604516750727303375469333819483373689308461864895 657
UVM_INFO @ 2882198614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) 2 test runs
aes_core_fi 30860526820686506777284269792755727200413512071117641991849806858905559750867 141
UVM_INFO @ 10019649830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 89799826565869351695471505232814814030627563244678609567707244910882836890854 143
UVM_INFO @ 10048148047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:93) [aes_core_fi_vseq] wait timeout occurred! 2 test runs
aes_core_fi 18664704935322348684133531376648825472912194374232434884538369755337460711299 147
UVM_INFO @ 10036737052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 69690873427500507935780223688466821983003658806255487350972605239140878353077 145
UVM_INFO @ 10135333214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1112): Assertion AesModeValid has failed 1 test run
aes_stress_all 107321376510077601654763238151573644221226872146851043737977078526891304672986 106308
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 440927424 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[2].gen_fsm_n.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 440927424 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[1].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_1.0/rtl/aes_control_fsm.sv,1180): (time 440927424 PS) Assertion tb.dut.u_aes_core.u_aes_control.gen_fsm[0].gen_fsm_p.u_aes_control_fsm_i.u_aes_control_fsm.AesModeValid has failed
UVM_ERROR @ 440927424 ps: (aes_core.sv:1112) [ASSERT FAILED] AesModeValid
UVM_FATAL (aes_base_vseq.sv:76) [aes_stress_all_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 71517883259656163781920737304422403345680970595405679704115676941554650438998 109
UVM_INFO @ 6237217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: aes_reg_block_extended.ctrl_shadowed reset value: * 1 test run
aes_shadow_reg_errors 49274948293888255500255001182706782377269511525224628732576637012001156124172 107
UVM_INFO @ 81746061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) 1 test run
aes_core_fi 63007125387193413526336252528634960204393385067990371976337180812438920631697 141
UVM_INFO @ 10022227525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
aes_cipher_fi 54089615459043189257876995147669900925092767964861238527679159588051810979742 147
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---