Simulation Results: clkmgr

 
06/06/2026 15:22:54 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.21 %
  • code
  • 98.91 %
  • assert
  • 95.90 %
  • func
  • 87.82 %
  • line
  • 99.33 %
  • branch
  • 99.16 %
  • cond
  • 96.06 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
74.48%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
clkmgr_smoke 1.390s 77.159us 10 10 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.670s 190.243us 1 1 100.00
csr_rw 5 5 100.00
clkmgr_csr_rw 1.400s 70.241us 5 5 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 7.640s 590.628us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.870s 141.179us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.580s 36.143us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
clkmgr_csr_rw 1.400s 70.241us 5 5 100.00
clkmgr_csr_aliasing 1.870s 141.179us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 10 10 100.00
clkmgr_peri 1.280s 52.806us 10 10 100.00
trans_enables 10 10 100.00
clkmgr_trans 1.970s 265.165us 10 10 100.00
extclk 10 10 100.00
clkmgr_extclk 1.440s 79.361us 10 10 100.00
clk_status 10 10 100.00
clkmgr_clk_status 1.110s 38.759us 10 10 100.00
jitter 10 10 100.00
clkmgr_smoke 1.390s 77.159us 10 10 100.00
frequency 10 10 100.00
clkmgr_frequency 21.680s 2480.997us 10 10 100.00
frequency_timeout 10 10 100.00
clkmgr_frequency_timeout 16.000s 2421.450us 10 10 100.00
frequency_overflow 10 10 100.00
clkmgr_frequency 21.680s 2480.997us 10 10 100.00
stress_all 10 10 100.00
clkmgr_stress_all 72.420s 10623.100us 10 10 100.00
alert_test 10 10 100.00
clkmgr_alert_test 1.270s 35.250us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
clkmgr_tl_errors 9.850s 2038.884us 25 25 100.00
tl_d_illegal_access 25 25 100.00
clkmgr_tl_errors 9.850s 2038.884us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
clkmgr_csr_hw_reset 1.670s 190.243us 1 1 100.00
clkmgr_csr_rw 1.400s 70.241us 5 5 100.00
clkmgr_csr_aliasing 1.870s 141.179us 1 1 100.00
clkmgr_same_csr_outstanding 1.550s 231.451us 5 5 100.00
tl_d_partial_access 12 12 100.00
clkmgr_csr_hw_reset 1.670s 190.243us 1 1 100.00
clkmgr_csr_rw 1.400s 70.241us 5 5 100.00
clkmgr_csr_aliasing 1.870s 141.179us 1 1 100.00
clkmgr_same_csr_outstanding 1.550s 231.451us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 19 30 63.33
clkmgr_sec_cm 66.180s 10453.405us 1 5 20.00
clkmgr_tl_intg_err 50.060s 10013.076us 18 25 72.00
shadow_reg_update_error 8 20 40.00
clkmgr_shadow_reg_errors 1147.920s 200000.000us 8 20 40.00
shadow_reg_read_clear_staged_value 8 20 40.00
clkmgr_shadow_reg_errors 1147.920s 200000.000us 8 20 40.00
shadow_reg_storage_error 8 20 40.00
clkmgr_shadow_reg_errors 1147.920s 200000.000us 8 20 40.00
shadowed_reset_glitch 8 20 40.00
clkmgr_shadow_reg_errors 1147.920s 200000.000us 8 20 40.00
shadow_reg_update_error_with_csr_rw 7 20 35.00
clkmgr_shadow_reg_errors_with_csr_rw 1136.390s 200000.000us 7 20 35.00
sec_cm_bus_integrity 18 25 72.00
clkmgr_tl_intg_err 50.060s 10013.076us 18 25 72.00
sec_cm_meas_clk_bkgn_chk 10 10 100.00
clkmgr_frequency 21.680s 2480.997us 10 10 100.00
sec_cm_timeout_clk_bkgn_chk 10 10 100.00
clkmgr_frequency_timeout 16.000s 2421.450us 10 10 100.00
sec_cm_meas_config_shadow 8 20 40.00
clkmgr_shadow_reg_errors 1147.920s 200000.000us 8 20 40.00
sec_cm_idle_intersig_mubi 10 10 100.00
clkmgr_idle_intersig_mubi 1.650s 110.182us 10 10 100.00
sec_cm_lc_ctrl_intersig_mubi 10 10 100.00
clkmgr_lc_ctrl_intersig_mubi 2.610s 410.779us 10 10 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 10 10 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.680s 170.468us 10 10 100.00
sec_cm_clk_handshake_intersig_mubi 9 10 90.00
clkmgr_clk_handshake_intersig_mubi 1.530s 89.956us 9 10 90.00
sec_cm_div_intersig_mubi 10 10 100.00
clkmgr_div_intersig_mubi 1.460s 97.883us 10 10 100.00
sec_cm_jitter_config_mubi 5 5 100.00
clkmgr_csr_rw 1.400s 70.241us 5 5 100.00
sec_cm_idle_ctr_redun 1 5 20.00
clkmgr_sec_cm 66.180s 10453.405us 1 5 20.00
sec_cm_meas_config_regwen 5 5 100.00
clkmgr_csr_rw 1.400s 70.241us 5 5 100.00
sec_cm_clk_ctrl_config_regwen 5 5 100.00
clkmgr_csr_rw 1.400s 70.241us 5 5 100.00
prim_count_check 1 5 20.00
clkmgr_sec_cm 66.180s 10453.405us 1 5 20.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 10 10 100.00
clkmgr_regwen 9.510s 1369.313us 10 10 100.00
stress_all_with_rand_reset 10 10 100.00
clkmgr_stress_all_with_rand_reset 78.210s 13889.757us 10 10 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 18 test runs
clkmgr_shadow_reg_errors 105880770036911334829060995120699805408448353295174877779081861547218774833508 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 17591260624397883538387545294337604399288064707371694255637332947931220686859 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 3495404956930287016193870657979759650671423025120303616609384502044121733941 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 21721373347253808549826440354033885297278855203624650429703781491910450224541 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 51682171359738860849508106486280435801628342977460875095573377537787027002642 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 64102900311390272126881338524474320887561115045874645931724448445735201166306 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 36178372312747587997378553228031513253778611694873410361947751698422114049421 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 59872145474280061533206364814151727961141993979519203670955101786878767675694 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 25609465406158472824251278687246363415010702695651644311253219782671019014072 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 51289298774223571712863547741002389414414069930647001059612645221420462371275 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 57066310108277921489667856360623687267367366389184906671263379811836866223349 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 53586528511644152628551814102831734979856534037288921604590198231229919454209 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 64077649672273949451820767003672558727198868170955558378892659574279680807332 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 115226002821011990951685198560579761750388424292502790817233270020208151413883 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 13495327736782877336113133793428481103184764869322997042804431247507435862741 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 47449773812780496835985357326397188208117588154560952941346800742015763611507 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 28786949481751797203024810376397587264983761917616769715879132315224273539777 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 83927006839268548519406649277986109602570133364500244752888763197793121796335 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 9 test runs
clkmgr_sec_cm 81327675824880806522856550798533135079499283431492844688824071018742684680759 237
UVM_INFO @ 10453404776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 88335812628869057794802374364628201771360234868910938307761792063620528763031 83
UVM_INFO @ 10041582884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 29874491511935384385933541371468124502845726996447273170686071117434808806775 86
UVM_INFO @ 10024167831 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 9998478001479815339803687679626892130781885553516799817959861504726563691108 163
UVM_INFO @ 10083746215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 15824147683516396996582611719808473894272442061660940832651064199692204100901 119
UVM_INFO @ 10049505214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 6788027000377808395163474003365336182221385138498455270151914843883246983676 93
UVM_INFO @ 10013076442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 81310865443790166911013181797392110822527659502170689848852475263718845089511 158
UVM_INFO @ 10096780946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 58481442259189057224996503134487982308616155392124281728874792830391390844243 93
UVM_INFO @ 10022871757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 27430612338354234609658478429984230591193092965892349173019725676519297617762 139
UVM_INFO @ 10116084808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 2 test runs
clkmgr_sec_cm 56082252315267850568947091379920135145665357382241012657857786126152187971696 94
UVM_INFO @ 22138555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 74973565377379888287010840257207988956333144733030302957379939437774491760073 91
UVM_INFO @ 17508926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.jitter_enable (addr=*) 2 test runs
clkmgr_shadow_reg_errors_with_csr_rw 102863298921734466826484401522675196746864480289449092450172300900989579210198 76
UVM_INFO @ 2069675053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 22012884452959620492951043857045552126063503305597263990213688613985024007188 76
UVM_INFO @ 2804488421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [*] vs * [*]) extclk_status mismatch 1 test run
clkmgr_clk_handshake_intersig_mubi 44464734497325437878461888189397368588307370509855058813471411372750489845578 74
UVM_INFO @ 16013536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 98550098441977553620348138374395239469377626400539732950401840601047250728641 75
UVM_INFO @ 45311529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.clk_hints_status (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 58366446363790222374748664446111912354979307258001327191697188048937135156161 75
UVM_INFO @ 2029432164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.extclk_status (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 79892122400600194165915692676471999978923439820619347835343394164322372282865 76
UVM_INFO @ 2129130880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.extclk_ctrl_regwen (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 24083312879541753511727901770973095560435801580121743634980278523940811183087 76
UVM_INFO @ 2200075260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.jitter_regwen (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 10257106457186733902090056052873674747193903175840926339064585764086707743917 75
UVM_INFO @ 2159072056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---