Simulation Results: csrng

 
06/06/2026 15:22:54 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.70 %
  • code
  • 96.20 %
  • assert
  • 97.16 %
  • func
  • 90.74 %
  • block
  • 98.53 %
  • line
  • 99.54 %
  • branch
  • 96.38 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
98.16%
V2S
98.99%
V3
10.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 25 25 100.00
csrng_smoke 10.000s 17.946us 25 25 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 31.000s 85.394us 1 1 100.00
csr_rw 5 5 100.00
csrng_csr_rw 30.000s 14.726us 5 5 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 39.000s 195.584us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 33.000s 128.124us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
csrng_csr_mem_rw_with_rand_reset 32.000s 98.554us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
csrng_csr_rw 30.000s 14.726us 5 5 100.00
csrng_csr_aliasing 33.000s 128.124us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 31.000s 706.135us 200 200 100.00
alerts 500 500 100.00
csrng_alert 42.000s 2492.642us 500 500 100.00
err 500 500 100.00
csrng_err 24.000s 85.477us 500 500 100.00
cmds 2 25 8.00
csrng_cmds 68.000s 2320.355us 2 25 8.00
life cycle 2 25 8.00
csrng_cmds 68.000s 2320.355us 2 25 8.00
stress_all 24 25 96.00
csrng_stress_all 1238.000s 98094.791us 24 25 96.00
intr_test 10 10 100.00
csrng_intr_test 21.000s 13.042us 10 10 100.00
alert_test 10 10 100.00
csrng_alert_test 31.000s 49.995us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
csrng_tl_errors 15.000s 1262.016us 25 25 100.00
tl_d_illegal_access 25 25 100.00
csrng_tl_errors 15.000s 1262.016us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
csrng_csr_hw_reset 31.000s 85.394us 1 1 100.00
csrng_csr_rw 30.000s 14.726us 5 5 100.00
csrng_csr_aliasing 33.000s 128.124us 1 1 100.00
csrng_same_csr_outstanding 22.000s 45.315us 5 5 100.00
tl_d_partial_access 12 12 100.00
csrng_csr_hw_reset 31.000s 85.394us 1 1 100.00
csrng_csr_rw 30.000s 14.726us 5 5 100.00
csrng_csr_aliasing 33.000s 128.124us 1 1 100.00
csrng_same_csr_outstanding 22.000s 45.315us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
csrng_sec_cm 14.000s 103.235us 5 5 100.00
csrng_tl_intg_err 16.000s 1409.502us 25 25 100.00
sec_cm_config_regwen 18 30 60.00
csrng_regwen 21.000s 13.640us 13 25 52.00
csrng_csr_rw 30.000s 14.726us 5 5 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 42.000s 2492.642us 500 500 100.00
sec_cm_intersig_mubi 24 25 96.00
csrng_stress_all 1238.000s 98094.791us 24 25 96.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 31.000s 706.135us 200 200 100.00
csrng_err 24.000s 85.477us 500 500 100.00
csrng_sec_cm 14.000s 103.235us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 31.000s 706.135us 200 200 100.00
csrng_err 24.000s 85.477us 500 500 100.00
csrng_sec_cm 14.000s 103.235us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 31.000s 706.135us 200 200 100.00
csrng_err 24.000s 85.477us 500 500 100.00
csrng_sec_cm 14.000s 103.235us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 31.000s 706.135us 200 200 100.00
csrng_err 24.000s 85.477us 500 500 100.00
csrng_sec_cm 14.000s 103.235us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 31.000s 706.135us 200 200 100.00
csrng_err 24.000s 85.477us 500 500 100.00
csrng_sec_cm 14.000s 103.235us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 42.000s 2492.642us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 31.000s 706.135us 200 200 100.00
csrng_err 24.000s 85.477us 500 500 100.00
sec_cm_constants_lc_gated 24 25 96.00
csrng_stress_all 1238.000s 98094.791us 24 25 96.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 42.000s 2492.642us 500 500 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
csrng_tl_intg_err 16.000s 1409.502us 25 25 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 31.000s 706.135us 200 200 100.00
csrng_err 24.000s 85.477us 500 500 100.00
csrng_sec_cm 14.000s 103.235us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 31.000s 706.135us 200 200 100.00
csrng_err 24.000s 85.477us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 31.000s 706.135us 200 200 100.00
csrng_err 24.000s 85.477us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 31.000s 706.135us 200 200 100.00
csrng_err 24.000s 85.477us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 31.000s 706.135us 200 200 100.00
csrng_err 24.000s 85.477us 500 500 100.00
csrng_sec_cm 14.000s 103.235us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 31.000s 706.135us 200 200 100.00
csrng_err 24.000s 85.477us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 10 10.00
csrng_stress_all_with_rand_reset 3601.000s 0.000us 1 10 10.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 21 test runs
csrng_cmds 50811761018247176404172376446178151028875439291626599988480826343760347789784 100
UVM_INFO @ 368015849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 87656893807852815741426710743365754539829591099482043891055993486617430034622 100
UVM_INFO @ 89837538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 1706891696758592935043160678222838475748277928759786560051915231341215018528 100
UVM_INFO @ 53214611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 103521758400991547186294197338032040180992430677350819705038007947141231113528 100
UVM_INFO @ 26673645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 90175568321536540745776664338874780028192916367794211695508607388329567567824 100
UVM_INFO @ 222060019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 70591781213824241368556565836790928420521004728362357247164876072375179561911 100
UVM_INFO @ 246637104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 112136571886249090969589863931523972000242547617025249307094604659442811230712 100
UVM_INFO @ 76191083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 6632331956208000702517823472808285567220255209303902039014701685906979335315 100
UVM_INFO @ 66986300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 10860196426679621525384542043315534792257239271515444901026023442997253925003 100
UVM_INFO @ 6400455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 38480439311041534616694023278782947875508576693218189227622151519549700486220 100
UVM_INFO @ 6446172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 64435509529020184425275739972831236716726809780423625481728760171831296691790 100
UVM_INFO @ 122405303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 13187384963284516098326669869887420925667019580660379466035435732033440975578 100
UVM_INFO @ 338342181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 77010681931940214045523937582481504702512526416458884155334705233314370759710 100
UVM_INFO @ 22345279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 2664981523310992857936969096982080175293516826650343190633839999795370822912 100
UVM_INFO @ 73762404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 77251599023188567980584446318258466568836755608637612623143424814300690891988 100
UVM_INFO @ 89377031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 20619042438631454136602544696175197937989406030860372326338288071691507852660 100
UVM_INFO @ 97525996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 13533077594700066455993647402653675820060422238681821297722825665737880638503 100
UVM_INFO @ 183458903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 110167614919256909155110159458066136046438547131996914327566865273328154728542 110
UVM_INFO @ 67265132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 107449114768334366940697901282753870691259296866307448439590633962204380630138 100
UVM_INFO @ 43850716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 56004352003488663778661510067175080094242886958852560824993412419078554704058 100
UVM_INFO @ 168652323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 88775750952119200726176764848311599378828059525579317363381443626363991955936 100
UVM_INFO @ 48884158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 10 test runs
csrng_regwen 14394286380605920040163285112944758735437809871697771481046238583321009515178 99
UVM_INFO @ 5072156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 100478684949188022680863364241724243526721675284144172634158700198819708927344 99
UVM_INFO @ 10859185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 86259867671042852127426132692442447455972439199798424665632324404040326764332 99
UVM_INFO @ 10288087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 97447342353209891294170597483838427054709339391861888197436340548860023810102 99
UVM_INFO @ 5060445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 17973220194206437711177744165451841348086178759470550482084359361412921850041 99
UVM_INFO @ 4899096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 19204144513469133658810770643262861595667761316328415431942900300596828872215 99
UVM_INFO @ 5024027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 54435157040218593116864775827971608672411389669563855068350234438082597904315 99
UVM_INFO @ 9746261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 73874103158072180872501005085462709131277016743332446893433397748817922632787 99
UVM_INFO @ 2954887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 80415996323578274560305098145068620139345774200490999570896065092371260316581 99
UVM_INFO @ 4478044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 84259590238191506223911180296748471783982814708259192893834791372550859606007 99
UVM_INFO @ 6514118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 7 test runs
csrng_stress_all_with_rand_reset 97747818111516018584427503626468599150901928821939186580522014392566738645021 None
csrng_stress_all_with_rand_reset 73014431895900061892419484677616603041699805264209103034935782810801556217012 None
csrng_stress_all_with_rand_reset 107703397302399729104860612536989248133994027498524190634140256583463353950743 None
csrng_stress_all_with_rand_reset 24637980429104912151200157106789157612853010658487782310830901550874761589434 None
csrng_stress_all_with_rand_reset 45324934379159128243012294756667482467650343031513427400935290966046521661533 None
csrng_stress_all_with_rand_reset 27097207527721946793569686402989775205450098730152067164564573563325719060817 None
csrng_stress_all_with_rand_reset 624290431374441077506898078726969985584041843300959122187620433221191648363 None
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started 2 test runs
csrng_stress_all_with_rand_reset 111849703376748538419778475330121828335677768709707990704042722022436319173660 105
UVM_INFO @ 10764144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 14630984621882196696334659751134601691749262122539966807897465942677326559991 104
UVM_INFO @ 72135092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE 2 test runs
csrng_regwen 104183995507132031584458591357681548452606290793873048386936215271288787768399 99
UVM_INFO @ 2883867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 87586425355658490356089361225846067836724313802367779245316101362443131675141 99
UVM_INFO @ 11297846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 1 test run
csrng_stress_all 107450919794112142465905311407831641398944484229364087612640846530715795964063 127
UVM_INFO @ 6808585474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:429) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: csrng_reg_block.genbits 1 test run
csrng_cmds 11512171744932095860836404813641539014759835721997565184800588515353544385369 103
UVM_INFO @ 65707452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_scoreboard.sv:640) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [*] vs * [*]) 1 test run
csrng_cmds 115513959862866323921931944931317721448971554834852663597216569688826640549658 109
UVM_INFO @ 128230258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---