Simulation Results

Simulation Results: edn/edn0

06/06/2026 15:22:54 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
95.64 %

code
95.37 %

assert
98.70 %

func
92.86 %

line
98.91 %

branch
96.51 %

cond
93.96 %

toggle
97.17 %

FSM
90.32 %

Validation stages

V1		100.00%
V2		98.68%
V2S		100.00%
V3		80.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	edn_smoke	1.460s	35.936us	10	10	100.00
csr_hw_reset				1	1	100.00
	edn_csr_hw_reset	1.410s	22.588us	1	1	100.00
csr_rw				5	5	100.00
	edn_csr_rw	1.430s	24.099us	5	5	100.00
csr_bit_bash				1	1	100.00
	edn_csr_bit_bash	5.070s	322.859us	1	1	100.00
csr_aliasing				1	1	100.00
	edn_csr_aliasing	1.580s	30.690us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	edn_csr_mem_rw_with_rand_reset	2.290s	27.382us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	edn_csr_rw	1.430s	24.099us	5	5	100.00
	edn_csr_aliasing	1.580s	30.690us	1	1	100.00

599/607 passed

98.68 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
firmware				100	100	100.00
	edn_genbits	3.030s	318.423us	100	100	100.00
csrng_commands				100	100	100.00
	edn_genbits	3.030s	318.423us	100	100	100.00
genbits				100	100	100.00
	edn_genbits	3.030s	318.423us	100	100	100.00
interrupts				20	20	100.00
	edn_intr	1.510s	23.895us	20	20	100.00
alerts				200	200	100.00
	edn_alert	1.730s	122.651us	200	200	100.00
errs				100	100	100.00
	edn_err	1.790s	57.346us	100	100	100.00
disable				92	100	92.00
	edn_disable	1.380s	11.765us	50	50	100.00
	edn_disable_auto_req_mode	17.100s	500.000us	42	50	84.00
stress_all				30	30	100.00
	edn_stress_all	6.050s	292.894us	30	30	100.00
intr_test				10	10	100.00
	edn_intr_test	1.330s	30.945us	10	10	100.00
alert_test				10	10	100.00
	edn_alert_test	1.340s	33.953us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	edn_tl_errors	3.420s	122.406us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	edn_tl_errors	3.420s	122.406us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	edn_csr_hw_reset	1.410s	22.588us	1	1	100.00
	edn_csr_rw	1.430s	24.099us	5	5	100.00
	edn_csr_aliasing	1.580s	30.690us	1	1	100.00
	edn_same_csr_outstanding	1.940s	72.097us	5	5	100.00
tl_d_partial_access				12	12	100.00
	edn_csr_hw_reset	1.410s	22.588us	1	1	100.00
	edn_csr_rw	1.430s	24.099us	5	5	100.00
	edn_csr_aliasing	1.580s	30.690us	1	1	100.00
	edn_same_csr_outstanding	1.940s	72.097us	5	5	100.00

V2S

235/235 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	edn_sec_cm	7.700s	2831.583us	5	5	100.00
	edn_tl_intg_err	2.590s	107.696us	25	25	100.00
sec_cm_config_regwen				5	5	100.00
	edn_regwen	1.570s	17.694us	5	5	100.00
sec_cm_config_mubi				200	200	100.00
	edn_alert	1.730s	122.651us	200	200	100.00
sec_cm_main_sm_fsm_sparse				5	5	100.00
	edn_sec_cm	7.700s	2831.583us	5	5	100.00
sec_cm_ack_sm_fsm_sparse				5	5	100.00
	edn_sec_cm	7.700s	2831.583us	5	5	100.00
sec_cm_fifo_ctr_redun				5	5	100.00
	edn_sec_cm	7.700s	2831.583us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	edn_sec_cm	7.700s	2831.583us	5	5	100.00
sec_cm_main_sm_ctr_local_esc				205	205	100.00
	edn_alert	1.730s	122.651us	200	200	100.00
	edn_sec_cm	7.700s	2831.583us	5	5	100.00
sec_cm_cs_rdata_bus_consistency				200	200	100.00
	edn_alert	1.730s	122.651us	200	200	100.00
sec_cm_tile_link_bus_integrity				25	25	100.00
	edn_tl_intg_err	2.590s	107.696us	25	25	100.00

24/30 passed

80.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				24	30	80.00
	edn_stress_all_with_rand_reset	103.730s	5189.415us	24	30	80.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				6 test runs
	edn_disable_auto_req_mode	54402089429409792607509565267703095880383170075255678997312051088831853279316	88	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	15292732756674310465128225985164386535175599203284712437734061243815906126942	88	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	53844606960582245831755706345312673222082326772523078589828897572897961251423	88	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	110833036149101738916413750808813125937740164595399913504771091546949048257063	88	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	636837353403453157406922226143418427229692956405564442483755030438789214129	88	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	59992061436975621653942588038975390224742065104977853536471790873601592351492	88	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				6 test runs
	edn_stress_all_with_rand_reset	76597234702584355260559650915687394631946947196550015523868606665485911857351	128	UVM_INFO @ 992980230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	27063678202780441464581936917411767075540561751980269008549160776259264043858	200	UVM_INFO @ 2083433332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	99530213449813238925804261074632076267738476278955239366224880195845835313949	153	UVM_INFO @ 1032012494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	34885346532201286480837231289261254715186010752089011997040111138219323734029	145	UVM_INFO @ 585787134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	34648819626191973986995222843228682514841964139250280458684269097626988552363	202	UVM_INFO @ 2498188626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	51274972331055470799334689205960091696299414369348994915120026386678240199157	305	UVM_INFO @ 3226360001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.				2 test runs
	edn_disable_auto_req_mode	109088626282222223463934139056653120321522921948012594198713007615592583414034	88	UVM_INFO @ 73539131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	24540131408302457594018317175854822231669250603487031403754455319481086157414	88	UVM_INFO @ 24563587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---