Simulation Results

Simulation Results: edn/edn1

06/06/2026 15:22:54 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
95.53 %

code
95.66 %

assert
98.70 %

func
92.23 %

line
98.48 %

branch
94.59 %

cond
94.85 %

toggle
96.08 %

FSM
94.32 %

Validation stages

V1		100.00%
V2		98.85%
V2S		100.00%
V3		86.67%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	edn_smoke	1.230s	20.660us	10	10	100.00
csr_hw_reset				1	1	100.00
	edn_csr_hw_reset	1.090s	14.362us	1	1	100.00
csr_rw				5	5	100.00
	edn_csr_rw	1.100s	49.955us	5	5	100.00
csr_bit_bash				1	1	100.00
	edn_csr_bit_bash	2.610s	143.791us	1	1	100.00
csr_aliasing				1	1	100.00
	edn_csr_aliasing	1.870s	78.643us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	edn_csr_mem_rw_with_rand_reset	1.610s	95.221us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	edn_csr_rw	1.100s	49.955us	5	5	100.00
	edn_csr_aliasing	1.870s	78.643us	1	1	100.00

600/607 passed

98.85 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
firmware				100	100	100.00
	edn_genbits	8.480s	1364.512us	100	100	100.00
csrng_commands				100	100	100.00
	edn_genbits	8.480s	1364.512us	100	100	100.00
genbits				100	100	100.00
	edn_genbits	8.480s	1364.512us	100	100	100.00
interrupts				20	20	100.00
	edn_intr	1.240s	22.834us	20	20	100.00
alerts				200	200	100.00
	edn_alert	1.620s	53.314us	200	200	100.00
errs				100	100	100.00
	edn_err	1.460s	105.540us	100	100	100.00
disable				93	100	93.00
	edn_disable	1.260s	13.930us	50	50	100.00
	edn_disable_auto_req_mode	4.070s	500.000us	43	50	86.00
stress_all				30	30	100.00
	edn_stress_all	6.630s	616.934us	30	30	100.00
intr_test				10	10	100.00
	edn_intr_test	1.180s	36.063us	10	10	100.00
alert_test				10	10	100.00
	edn_alert_test	1.140s	16.224us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	edn_tl_errors	3.810s	340.675us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	edn_tl_errors	3.810s	340.675us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	edn_csr_hw_reset	1.090s	14.362us	1	1	100.00
	edn_csr_rw	1.100s	49.955us	5	5	100.00
	edn_csr_aliasing	1.870s	78.643us	1	1	100.00
	edn_same_csr_outstanding	1.260s	19.550us	5	5	100.00
tl_d_partial_access				12	12	100.00
	edn_csr_hw_reset	1.090s	14.362us	1	1	100.00
	edn_csr_rw	1.100s	49.955us	5	5	100.00
	edn_csr_aliasing	1.870s	78.643us	1	1	100.00
	edn_same_csr_outstanding	1.260s	19.550us	5	5	100.00

V2S

235/235 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	edn_sec_cm	3.990s	1372.905us	5	5	100.00
	edn_tl_intg_err	2.730s	104.220us	25	25	100.00
sec_cm_config_regwen				5	5	100.00
	edn_regwen	1.000s	51.936us	5	5	100.00
sec_cm_config_mubi				200	200	100.00
	edn_alert	1.620s	53.314us	200	200	100.00
sec_cm_main_sm_fsm_sparse				5	5	100.00
	edn_sec_cm	3.990s	1372.905us	5	5	100.00
sec_cm_ack_sm_fsm_sparse				5	5	100.00
	edn_sec_cm	3.990s	1372.905us	5	5	100.00
sec_cm_fifo_ctr_redun				5	5	100.00
	edn_sec_cm	3.990s	1372.905us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	edn_sec_cm	3.990s	1372.905us	5	5	100.00
sec_cm_main_sm_ctr_local_esc				205	205	100.00
	edn_alert	1.620s	53.314us	200	200	100.00
	edn_sec_cm	3.990s	1372.905us	5	5	100.00
sec_cm_cs_rdata_bus_consistency				200	200	100.00
	edn_alert	1.620s	53.314us	200	200	100.00
sec_cm_tile_link_bus_integrity				25	25	100.00
	edn_tl_intg_err	2.730s	104.220us	25	25	100.00

26/30 passed

86.67 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				26	30	86.67
	edn_stress_all_with_rand_reset	89.550s	19583.634us	26	30	86.67

Error Messages

	Test	seed	line	log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				5 test runs
	edn_disable_auto_req_mode	6803951660302142380768683996507395757590754431007748551229457722241476190535	88	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	70661718134541642350536800997200306503913313910098308853628245829627251269551	89	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	8267268309311492922731406731033151448574000669692404276606828032255145749180	89	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	111752330237898732675717170938914176031289357492171913489445401678372494330878	89	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	40854785901197265895057961781823444593173844381741863674473234652967318909851	89	UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				3 test runs
	edn_stress_all_with_rand_reset	16572692794829364442445887917760684070821918210274661347692729458270811319156	293	UVM_INFO @ 2744660061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	106769998961375928867145165705085099652090554188987650009225307620689093098584	179	UVM_INFO @ 1017353874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_stress_all_with_rand_reset	17352906079265859089302694622835073922164690622229653592807243307566256018496	133	UVM_INFO @ 745695031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx.				2 test runs
	edn_disable_auto_req_mode	61922634655338864606157758170984192027101398510178823031866445583486522444387	88	UVM_INFO @ 35695272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	edn_disable_auto_req_mode	109661270462055717181447229813676416288569103427214097201234255381758332368371	88	UVM_INFO @ 67465449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Error-[FCIBH] Illegal bin hit				1 test run
	edn_stress_all_with_rand_reset	60136720129546401076533655091310870181026722370420258978278654496988195275315	316	/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25 csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg" VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 2694738704 ps, Illegal state bin il of coverpoint csrng_cmd_cp in covergroup