| V1 |
|
100.00% |
| V2 |
|
94.27% |
| V2S |
|
100.00% |
| V3 |
|
50.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 40 | 40 | 100.00 | |||
| gpio_smoke | 1.710s | 158.484us | 10 | 10 | 100.00 | |
| gpio_smoke_no_pullup_pulldown | 1.830s | 245.873us | 10 | 10 | 100.00 | |
| gpio_smoke_en_cdc_prim | 1.630s | 45.846us | 10 | 10 | 100.00 | |
| gpio_smoke_no_pullup_pulldown_en_cdc_prim | 1.780s | 1118.740us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| gpio_csr_hw_reset | 1.010s | 155.483us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| gpio_csr_rw | 0.880s | 23.707us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| gpio_csr_bit_bash | 3.060s | 1129.431us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| gpio_csr_aliasing | 1.180s | 31.384us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| gpio_csr_mem_rw_with_rand_reset | 1.520s | 24.932us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| gpio_csr_rw | 0.880s | 23.707us | 5 | 5 | 100.00 | |
| gpio_csr_aliasing | 1.180s | 31.384us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| direct_and_masked_out | 20 | 20 | 100.00 | |||
| gpio_random_dout_din | 1.570s | 27.817us | 10 | 10 | 100.00 | |
| gpio_random_dout_din_no_pullup_pulldown | 1.700s | 77.899us | 10 | 10 | 100.00 | |
| out_in_regs_read_write | 10 | 10 | 100.00 | |||
| gpio_dout_din_regs_random_rw | 1.310s | 44.010us | 10 | 10 | 100.00 | |
| gpio_interrupt_programming | 10 | 10 | 100.00 | |||
| gpio_intr_rand_pgm | 1.890s | 109.739us | 10 | 10 | 100.00 | |
| random_interrupt_trigger | 10 | 10 | 100.00 | |||
| gpio_rand_intr_trigger | 3.690s | 400.654us | 10 | 10 | 100.00 | |
| interrupt_and_noise_filter | 10 | 10 | 100.00 | |||
| gpio_intr_with_filter_rand_intr_event | 3.440s | 75.294us | 10 | 10 | 100.00 | |
| noise_filter_stress | 10 | 10 | 100.00 | |||
| gpio_filter_stress | 15.840s | 3139.416us | 10 | 10 | 100.00 | |
| regs_long_reads_and_writes | 10 | 10 | 100.00 | |||
| gpio_random_long_reg_writes_reg_reads | 5.930s | 3239.719us | 10 | 10 | 100.00 | |
| full_random | 10 | 10 | 100.00 | |||
| gpio_full_random | 1.280s | 800.516us | 10 | 10 | 100.00 | |
| stress_all | 1 | 10 | 10.00 | |||
| gpio_stress_all | 66.350s | 7805.010us | 1 | 10 | 10.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| gpio_alert_test | 0.940s | 20.462us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| gpio_intr_test | 0.940s | 28.705us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| gpio_tl_errors | 2.950s | 904.231us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| gpio_tl_errors | 2.950s | 904.231us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| gpio_csr_rw | 0.880s | 23.707us | 5 | 5 | 100.00 | |
| gpio_same_csr_outstanding | 1.140s | 211.825us | 5 | 5 | 100.00 | |
| gpio_csr_aliasing | 1.180s | 31.384us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 1.010s | 155.483us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| gpio_csr_rw | 0.880s | 23.707us | 5 | 5 | 100.00 | |
| gpio_same_csr_outstanding | 1.140s | 211.825us | 5 | 5 | 100.00 | |
| gpio_csr_aliasing | 1.180s | 31.384us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 1.010s | 155.483us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 30 | 30 | 100.00 | |||
| gpio_tl_intg_err | 1.960s | 146.329us | 25 | 25 | 100.00 | |
| gpio_sec_cm | 1.210s | 139.627us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| gpio_tl_intg_err | 1.960s | 146.329us | 25 | 25 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| straps_data | 10 | 10 | 100.00 | |||
| gpio_rand_straps | 0.940s | 45.565us | 10 | 10 | 100.00 | |
| stress_all_with_rand_reset | 0 | 10 | 0.00 | |||
| gpio_stress_all_with_rand_reset | 10.090s | 7244.760us | 0 | 10 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (gpio_scoreboard.sv:216) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | 9 test runs | |||
| gpio_stress_all | 43482736825004056841405808688056194919068524875130611688751308188158295458757 | 1024 |
UVM_INFO @ 4606999946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 50965927437001700585047129932726738378391782810570682660886298724071628007830 | 83 |
UVM_INFO @ 2938065334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 102349336246540833918188263762646272182786389569000862194343726448766335235837 | 77 |
UVM_INFO @ 194360181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 18964986384658134901743660295897175240604019793276061404530953132675139597920 | 710 |
UVM_INFO @ 3685898736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 88369840496535226529603942642895627353559377435950671207602979370717256560508 | 1791 |
UVM_INFO @ 7805010297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 20696984767043087642631282171084947771390347051286426214954686287198034004068 | 128 |
UVM_INFO @ 119458025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 112803890639422464366029342088039407109726519171952123807651027029621787172857 | 594 |
UVM_INFO @ 1089244509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 15786242129571447030158940064867542217094266140399643390363105347059412823250 | 660 |
UVM_INFO @ 483357933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 88601841663037081417694418441436097086373818681432106956212262904202134171215 | 245 |
UVM_INFO @ 1286584706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1220) [gpio_common_vseq] Check failed (vseq_done) | 8 test runs | |||
| gpio_stress_all_with_rand_reset | 107801946192519818739288078185515236430702710168816047561611486415814236726114 | 80 |
UVM_INFO @ 19639440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 39384745842207476432760840735909397188203705029744999464605286258936440449478 | 80 |
UVM_INFO @ 32509925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 101568352322800605879663865792321393514173692602940929539720150120722296726470 | 80 |
UVM_INFO @ 26654417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 103120000028407702097190264389091764799107541161312553332297162455272400176320 | 80 |
UVM_INFO @ 22765147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 62758126786707409299308399935359708767171315328339188683907153278793618646276 | 80 |
UVM_INFO @ 125203017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 31685128112979813016398586059341018178849076827317459617186349484350846181903 | 82 |
UVM_INFO @ 44853989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 105499001909979405412961659035124822449550862256842345255018486805718111048696 | 80 |
UVM_INFO @ 16897364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 25421126028105054507809515335340407759757103901496933367209005607271923539885 | 250 |
UVM_INFO @ 7244759963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* | 2 test runs | |||
| gpio_stress_all_with_rand_reset | 51880008338489008284219130110769223562513518469148452913383760624290678908710 | 231 |
UVM_INFO @ 4305728467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 58363679788359722464247805577004437621900481256585959361998735711496371301723 | 78 |
UVM_INFO @ 6795911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|