Simulation Results: hmac

 
06/06/2026 15:22:54 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 99.47 %
  • code
  • 99.29 %
  • assert
  • 99.12 %
  • func
  • 100.00 %
  • line
  • 99.90 %
  • branch
  • 99.83 %
  • cond
  • 96.74 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
98.57%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 9.990s 7784.143us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.110s 29.269us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 1.320s 187.491us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 14.900s 1603.753us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.480s 1676.266us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 390.250s 494830.249us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 1.320s 187.491us 5 5 100.00
hmac_csr_aliasing 6.480s 1676.266us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 93.350s 17263.157us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 81.830s 1511.119us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 253.030s 15172.748us 30 30 100.00
hmac_test_sha384_vectors 542.230s 73102.616us 75 75 100.00
hmac_test_sha512_vectors 549.580s 17065.469us 75 75 100.00
hmac_test_hmac256_vectors 15.790s 2299.811us 50 50 100.00
hmac_test_hmac384_vectors 16.130s 965.016us 60 60 100.00
hmac_test_hmac512_vectors 18.330s 1524.848us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 31.800s 670.537us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1232.060s 7141.052us 10 10 100.00
error 10 10 100.00
hmac_error 121.030s 39696.035us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 124.540s 51419.880us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 9.990s 7784.143us 10 10 100.00
hmac_long_msg 93.350s 17263.157us 10 10 100.00
hmac_back_pressure 81.830s 1511.119us 25 25 100.00
hmac_datapath_stress 1232.060s 7141.052us 10 10 100.00
hmac_burst_wr 31.800s 670.537us 50 50 100.00
hmac_stress_all 3280.260s 98903.668us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 9.990s 7784.143us 10 10 100.00
hmac_long_msg 93.350s 17263.157us 10 10 100.00
hmac_back_pressure 81.830s 1511.119us 25 25 100.00
hmac_datapath_stress 1232.060s 7141.052us 10 10 100.00
hmac_wipe_secret 124.540s 51419.880us 10 10 100.00
hmac_test_sha256_vectors 253.030s 15172.748us 30 30 100.00
hmac_test_sha384_vectors 542.230s 73102.616us 75 75 100.00
hmac_test_sha512_vectors 549.580s 17065.469us 75 75 100.00
hmac_test_hmac256_vectors 15.790s 2299.811us 50 50 100.00
hmac_test_hmac384_vectors 16.130s 965.016us 60 60 100.00
hmac_test_hmac512_vectors 18.330s 1524.848us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 9.990s 7784.143us 10 10 100.00
hmac_long_msg 93.350s 17263.157us 10 10 100.00
hmac_back_pressure 81.830s 1511.119us 25 25 100.00
hmac_datapath_stress 1232.060s 7141.052us 10 10 100.00
hmac_burst_wr 31.800s 670.537us 50 50 100.00
hmac_error 121.030s 39696.035us 10 10 100.00
hmac_wipe_secret 124.540s 51419.880us 10 10 100.00
hmac_test_sha256_vectors 253.030s 15172.748us 30 30 100.00
hmac_test_sha384_vectors 542.230s 73102.616us 75 75 100.00
hmac_test_sha512_vectors 549.580s 17065.469us 75 75 100.00
hmac_test_hmac256_vectors 15.790s 2299.811us 50 50 100.00
hmac_test_hmac384_vectors 16.130s 965.016us 60 60 100.00
hmac_test_hmac512_vectors 18.330s 1524.848us 75 75 100.00
hmac_stress_all 3280.260s 98903.668us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 3280.260s 98903.668us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 0.910s 53.822us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 0.960s 20.772us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 3.880s 213.736us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 3.880s 213.736us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 1.110s 29.269us 1 1 100.00
hmac_csr_rw 1.320s 187.491us 5 5 100.00
hmac_csr_aliasing 6.480s 1676.266us 1 1 100.00
hmac_same_csr_outstanding 2.770s 214.171us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 1.110s 29.269us 1 1 100.00
hmac_csr_rw 1.320s 187.491us 5 5 100.00
hmac_csr_aliasing 6.480s 1676.266us 1 1 100.00
hmac_same_csr_outstanding 2.770s 214.171us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 1.500s 166.773us 5 5 100.00
hmac_tl_intg_err 4.650s 451.462us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 4.650s 451.462us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 9.990s 7784.143us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 7.390s 1311.230us 25 25 100.00
stress_all_with_rand_reset 34 35 97.14
hmac_stress_all_with_rand_reset 366.670s 4247.962us 34 35 97.14
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.950s 13.185us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:465) [hmac_common_vseq] wait timeout occurred! 1 test run
hmac_stress_all_with_rand_reset 36259743869961036785810690814841498680691919826496635765227201208629024042059 18471
UVM_INFO @ 58619519130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---