Simulation Results: keymgr

 
06/06/2026 15:22:54 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.89 %
  • code
  • 98.96 %
  • assert
  • 97.72 %
  • func
  • 90.99 %
  • line
  • 99.20 %
  • branch
  • 99.00 %
  • cond
  • 98.16 %
  • toggle
  • 98.44 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.83%
V2S
99.08%
V3
55.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 30 30 100.00
keymgr_smoke 18.910s 2914.547us 30 30 100.00
random 30 30 100.00
keymgr_random 113.750s 24242.728us 30 30 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.110s 65.282us 1 1 100.00
csr_rw 5 5 100.00
keymgr_csr_rw 1.860s 200.949us 5 5 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 10.840s 572.766us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 3.770s 328.142us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
keymgr_csr_mem_rw_with_rand_reset 1.840s 26.517us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
keymgr_csr_rw 1.860s 200.949us 5 5 100.00
keymgr_csr_aliasing 3.770s 328.142us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 50 50 100.00
keymgr_cfg_regwen 80.330s 8762.301us 50 50 100.00
sideload 80 80 100.00
keymgr_sideload 47.070s 6257.025us 20 20 100.00
keymgr_sideload_kmac 13.860s 918.972us 20 20 100.00
keymgr_sideload_aes 15.640s 563.057us 20 20 100.00
keymgr_sideload_otbn 21.610s 859.212us 20 20 100.00
direct_to_disabled_state 30 30 100.00
keymgr_direct_to_disabled 15.290s 2970.256us 30 30 100.00
lc_disable 47 50 94.00
keymgr_lc_disable 7.920s 689.374us 47 50 94.00
kmac_error_response 20 20 100.00
keymgr_kmac_rsp_err 8.560s 373.848us 20 20 100.00
invalid_sw_input 20 20 100.00
keymgr_sw_invalid_input 49.120s 7828.869us 20 20 100.00
invalid_hw_input 50 50 100.00
keymgr_hwsw_invalid_input 66.560s 40991.002us 50 50 100.00
sync_async_fault_cross 20 20 100.00
keymgr_sync_async_fault_cross 15.230s 2652.162us 20 20 100.00
stress_all 48 50 96.00
keymgr_stress_all 826.440s 109228.573us 48 50 96.00
intr_test 10 10 100.00
keymgr_intr_test 1.160s 23.483us 10 10 100.00
alert_test 10 10 100.00
keymgr_alert_test 1.210s 102.336us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
keymgr_tl_errors 3.850s 128.734us 25 25 100.00
tl_d_illegal_access 25 25 100.00
keymgr_tl_errors 3.850s 128.734us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
keymgr_csr_hw_reset 1.110s 65.282us 1 1 100.00
keymgr_csr_rw 1.860s 200.949us 5 5 100.00
keymgr_csr_aliasing 3.770s 328.142us 1 1 100.00
keymgr_same_csr_outstanding 2.290s 288.913us 5 5 100.00
tl_d_partial_access 12 12 100.00
keymgr_csr_hw_reset 1.110s 65.282us 1 1 100.00
keymgr_csr_rw 1.860s 200.949us 5 5 100.00
keymgr_csr_aliasing 3.770s 328.142us 1 1 100.00
keymgr_same_csr_outstanding 2.290s 288.913us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 18.450s 1522.505us 5 5 100.00
tl_intg_err 30 30 100.00
keymgr_sec_cm 18.450s 1522.505us 5 5 100.00
keymgr_tl_intg_err 8.970s 5135.439us 25 25 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 6.070s 644.916us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 6.070s 644.916us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 6.070s 644.916us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 6.070s 644.916us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 17.940s 7403.255us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 18.450s 1522.505us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 18.450s 1522.505us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
keymgr_tl_intg_err 8.970s 5135.439us 25 25 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 6.070s 644.916us 20 20 100.00
sec_cm_op_config_regwen 50 50 100.00
keymgr_cfg_regwen 80.330s 8762.301us 50 50 100.00
sec_cm_reseed_config_regwen 35 35 100.00
keymgr_random 113.750s 24242.728us 30 30 100.00
keymgr_csr_rw 1.860s 200.949us 5 5 100.00
sec_cm_sw_binding_config_regwen 35 35 100.00
keymgr_random 113.750s 24242.728us 30 30 100.00
keymgr_csr_rw 1.860s 200.949us 5 5 100.00
sec_cm_max_key_ver_config_regwen 35 35 100.00
keymgr_random 113.750s 24242.728us 30 30 100.00
keymgr_csr_rw 1.860s 200.949us 5 5 100.00
sec_cm_lc_ctrl_intersig_mubi 47 50 94.00
keymgr_lc_disable 7.920s 689.374us 47 50 94.00
sec_cm_constants_consistency 50 50 100.00
keymgr_hwsw_invalid_input 66.560s 40991.002us 50 50 100.00
sec_cm_intersig_consistency 50 50 100.00
keymgr_hwsw_invalid_input 66.560s 40991.002us 50 50 100.00
sec_cm_hw_key_sw_noaccess 30 30 100.00
keymgr_random 113.750s 24242.728us 30 30 100.00
sec_cm_output_keys_ctrl_redun 20 20 100.00
keymgr_sideload_protect 14.000s 962.425us 20 20 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 18.450s 1522.505us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 18.450s 1522.505us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 18.450s 1522.505us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 10.620s 242.110us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 47 50 94.00
keymgr_lc_disable 7.920s 689.374us 47 50 94.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 18.450s 1522.505us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 18.450s 1522.505us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 18.450s 1522.505us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 10.620s 242.110us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 10.620s 242.110us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 18.450s 1522.505us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 10.620s 242.110us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 18.450s 1522.505us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 10.620s 242.110us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 11 20 55.00
keymgr_stress_all_with_rand_reset 17.890s 332.252us 11 20 55.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 9 test runs
keymgr_stress_all_with_rand_reset 92898349908825014741121994364659270962373031401685097525950731795519483564651 97
UVM_INFO @ 1485239623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 114623067819068230685702946348998128976204255912887341834804222903425019998426 214
UVM_INFO @ 417883544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 57254693902723235816221870124217993414034112733405466249666291600119721679210 147
UVM_INFO @ 107637423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 101357651146471879777287094110066171739068782872907829636743053392020678582181 465
UVM_INFO @ 192085543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 94892678905107563720639503066177256760770974889586465493016263911357311958199 806
UVM_INFO @ 1084855766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 76490363360558559665063795721611925903842057315601734190755577781268937812141 451
UVM_INFO @ 383419112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 77365178921552922303847157952478718568498292948084535433575203611567150131497 143
UVM_INFO @ 676349280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 105359497885742832019919877477591338154691310528268074852599658261781784114302 453
UVM_INFO @ 672058737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 45861171735422807946977183181386266090010815532712505125354213572328836980701 172
UVM_INFO @ 232150399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* 2 test runs
keymgr_stress_all 81341120492646622870130537606328802130303189372167153474243181610683454021717 2592
UVM_INFO @ 2887407684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all 113297112438321607342791912746838289410871338471898759224150157476939569270128 109
UVM_INFO @ 14810343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share0_output_* 2 test runs
keymgr_lc_disable 90414392484324184757953890201525355451828704233588126002860195307716579172250 264
UVM_INFO @ 319151707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_lc_disable 100547290219988295696452829785772381996675481239071885160587605971792080910694 390
UVM_INFO @ 83673708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share1_output_* 1 test run
keymgr_lc_disable 24957428058092323218803866286576229632198401090062075366942145304864637519867 103
UVM_INFO @ 40270246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---