Simulation Results: kmac/masked

 
06/06/2026 15:22:54 DVSim: v1.49.0 sha: 2348eb2 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.13 %
  • code
  • 94.69 %
  • assert
  • 98.70 %
  • func
  • 97.99 %
  • line
  • 99.25 %
  • branch
  • 97.10 %
  • cond
  • 94.81 %
  • toggle
  • 99.89 %
  • FSM
  • 82.39 %
Validation stages
V1
100.00%
V2
99.76%
V2S
98.82%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
kmac_smoke 88.620s 11081.689us 20 20 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.150s 23.262us 1 1 100.00
csr_rw 5 5 100.00
kmac_csr_rw 1.560s 32.560us 5 5 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 16.310s 1127.499us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 3.130s 274.080us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
kmac_csr_mem_rw_with_rand_reset 3.120s 78.407us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
kmac_csr_rw 1.560s 32.560us 5 5 100.00
kmac_csr_aliasing 3.130s 274.080us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 1.070s 30.602us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.310s 30.911us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 20 20 100.00
kmac_long_msg_and_output 5108.470s 485384.609us 20 20 100.00
burst_write 20 20 100.00
kmac_burst_write 1334.480s 70327.937us 20 20 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 3165.840s 218411.388us 5 5 100.00
kmac_test_vectors_sha3_256 2769.120s 218098.148us 5 5 100.00
kmac_test_vectors_sha3_384 1793.100s 144846.215us 5 5 100.00
kmac_test_vectors_sha3_512 1307.110s 54469.584us 5 5 100.00
kmac_test_vectors_shake_128 2323.330s 20854.464us 5 5 100.00
kmac_test_vectors_shake_256 420.240s 110962.664us 5 5 100.00
kmac_test_vectors_kmac 3.630s 139.187us 5 5 100.00
kmac_test_vectors_kmac_xof 3.880s 134.896us 5 5 100.00
sideload 20 20 100.00
kmac_sideload 515.980s 393612.468us 20 20 100.00
app 25 25 100.00
kmac_app 388.890s 23496.240us 25 25 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 337.290s 16520.656us 10 10 100.00
entropy_refresh 20 20 100.00
kmac_entropy_refresh 394.700s 30556.311us 20 20 100.00
error 20 20 100.00
kmac_error 512.670s 90328.944us 20 20 100.00
key_error 20 20 100.00
kmac_key_error 16.080s 8837.598us 20 20 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 9.040s 1124.359us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 55.600s 4920.209us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 15.000s 1564.144us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 43.680s 21712.715us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 57.620s 2005.545us 50 50 100.00
stress_all 19 20 95.00
kmac_stress_all 3087.110s 348570.899us 19 20 95.00
intr_test 10 10 100.00
kmac_intr_test 1.210s 21.691us 10 10 100.00
alert_test 10 10 100.00
kmac_alert_test 1.190s 19.716us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
kmac_tl_errors 5.010s 192.454us 25 25 100.00
tl_d_illegal_access 25 25 100.00
kmac_tl_errors 5.010s 192.454us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
kmac_csr_hw_reset 1.150s 23.262us 1 1 100.00
kmac_csr_rw 1.560s 32.560us 5 5 100.00
kmac_csr_aliasing 3.130s 274.080us 1 1 100.00
kmac_same_csr_outstanding 2.980s 575.734us 5 5 100.00
tl_d_partial_access 12 12 100.00
kmac_csr_hw_reset 1.150s 23.262us 1 1 100.00
kmac_csr_rw 1.560s 32.560us 5 5 100.00
kmac_csr_aliasing 3.130s 274.080us 1 1 100.00
kmac_same_csr_outstanding 2.980s 575.734us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.590s 159.938us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.590s 159.938us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.590s 159.938us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.590s 159.938us 20 20 100.00
shadow_reg_update_error_with_csr_rw 18 20 90.00
kmac_shadow_reg_errors_with_csr_rw 5.690s 227.837us 18 20 90.00
tl_intg_err 30 30 100.00
kmac_sec_cm 69.350s 68442.309us 5 5 100.00
kmac_tl_intg_err 5.890s 463.165us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
kmac_tl_intg_err 5.890s 463.165us 25 25 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 57.620s 2005.545us 50 50 100.00
sec_cm_sw_key_key_masking 20 20 100.00
kmac_smoke 88.620s 11081.689us 20 20 100.00
sec_cm_key_sideload 20 20 100.00
kmac_sideload 515.980s 393612.468us 20 20 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.590s 159.938us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 69.350s 68442.309us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 69.350s 68442.309us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 69.350s 68442.309us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 20 20 100.00
kmac_smoke 88.620s 11081.689us 20 20 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 57.620s 2005.545us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 69.350s 68442.309us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 321.900s 160892.004us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 20 20 100.00
kmac_smoke 88.620s 11081.689us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
kmac_stress_all_with_rand_reset 105.270s 13135.013us 10 10 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * 1 test run
kmac_shadow_reg_errors_with_csr_rw 95909858615477021642463690430074039449414054531176489611686482598493002809380 223
UVM_INFO @ 110981680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * 1 test run
kmac_stress_all 33416208256926132550150954517777843765352571031842659692268175955734269314360 257
UVM_INFO @ 104337964845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * 1 test run
kmac_shadow_reg_errors_with_csr_rw 67281599657714548697144624826171544241731306048007364920685264954183132462426 393
UVM_INFO @ 58307239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---